search for: pci_read_base

[PATCH 1/4] PCI: export pci_read_base and add pci_update_base Export pci_read_base; add pci_update_base to for PCI BAR update. Signed-off-by: Yu Zhao <yu.zhao at intel.com> Signed-off-by: Eddie Dong <eddie.dong at intel.com> --- drivers/pci/probe.c | 25 ++++++++-------- drivers/pci/setup-res.c | 74 +++++++++++...

[PATCH 1/4] PCI: export pci_read_base and add pci_update_base Export pci_read_base; add pci_update_base to for PCI BAR update. Signed-off-by: Yu Zhao <yu.zhao at intel.com> Signed-off-by: Eddie Dong <eddie.dong at intel.com> --- drivers/pci/probe.c | 25 ++++++++-------- drivers/pci/setup-res.c | 74 +++++++++++...

[PATCH 1/4] PCI: export pci_read_base and add pci_update_base Export pci_read_base; add pci_update_base to for PCI BAR update. Signed-off-by: Yu Zhao <yu.zhao at intel.com> Signed-off-by: Eddie Dong <eddie.dong at intel.com> --- drivers/pci/probe.c | 25 ++++++++-------- drivers/pci/setup-res.c | 74 +++++++++++...

...e { + pci_bar_unknown, /* Standard PCI BAR probe */ + pci_bar_io, /* An io port BAR */ + pci_bar_mem32, /* A 32-bit memory BAR */ + pci_bar_mem64, /* A 64-bit memory BAR */ + pci_bar_rom, /* A ROM BAR */ +}; + +extern int pci_read_base(struct pci_dev *dev, enum pci_bar_type type, + struct resource *res, unsigned int reg); +extern struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, + struct pci_dev *bridge, int busnr); + +#endif /* DRIVERS_PCI_H */ diff --git a/dr...

...e { + pci_bar_unknown, /* Standard PCI BAR probe */ + pci_bar_io, /* An io port BAR */ + pci_bar_mem32, /* A 32-bit memory BAR */ + pci_bar_mem64, /* A 64-bit memory BAR */ + pci_bar_rom, /* A ROM BAR */ +}; + +extern int pci_read_base(struct pci_dev *dev, enum pci_bar_type type, + struct resource *res, unsigned int reg); +extern struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, + struct pci_dev *bridge, int busnr); + +#endif /* DRIVERS_PCI_H */ diff --git a/dr...

...DDRESS_SPACE_IO) { @@ -224,16 +217,21 @@ static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) return pci_bar_mem32; } -/* - * If the type is not unknown, we assume that the lowest bit is 'enable'. - * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit. +/** + * pci_read_base - read a PCI BAR + * @dev: the PCI device + * @type: type of the BAR + * @res: resource buffer to be filled in + * @pos: BAR position in the config space + * + * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. */ -static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, +int pci_re...

...DDRESS_SPACE_IO) { @@ -224,16 +217,21 @@ static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) return pci_bar_mem32; } -/* - * If the type is not unknown, we assume that the lowest bit is 'enable'. - * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit. +/** + * pci_read_base - read a PCI BAR + * @dev: the PCI device + * @type: type of the BAR + * @res: resource buffer to be filled in + * @pos: BAR position in the config space + * + * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. */ -static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, +int pci_re...

...DDRESS_SPACE_IO) { @@ -224,16 +217,21 @@ static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) return pci_bar_mem32; } -/* - * If the type is not unknown, we assume that the lowest bit is 'enable'. - * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit. +/** + * pci_read_base - read a PCI BAR + * @dev: the PCI device + * @type: type of the BAR + * @res: resource buffer to be filled in + * @pos: BAR position in the config space + * + * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. */ -static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, +int pci_re...

...can control allocation of Virtual Functions via registers encapsulated in the capability. Following patches add SR-IOV capability support to the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective. [PATCH 1/4] PCI: export pci_read_base and add pci_update_base [PATCH 2/4] PCI: support ARI capability [PATCH 3/4] PCI: support SR-IOV capability [PATCH 4/4] PCI: document SR-IOV SR-IOV specification can be found at http://www.pcisig.com/members/downloads/specifications/iov/sr-iov1.0_11Sep07.pdf

...>stride = stride; + iov->align = pgsz << 12; + mutex_init(&iov->mutex); + + for (i = 0; i < PCI_IOV_NUM_BAR; i++) { + res = dev->resource + PCI_IOV_RESOURCES + i; + pos = iov->cap + PCI_IOV_BAR_0 + i * 4; + i += pci_read_base(dev, pci_bar_unknown, res, pos); + if (!res->flags) + continue; + res->flags &= ~IORESOURCE_SIZEALIGN; + res->end = res->start + resource_size(res) * total - 1; + } + + dev->iov = iov; + dev_info(&a...

...>stride = stride; + iov->align = pgsz << 12; + mutex_init(&iov->mutex); + + for (i = 0; i < PCI_IOV_NUM_BAR; i++) { + res = dev->resource + PCI_IOV_RESOURCES + i; + pos = iov->cap + PCI_IOV_BAR_0 + i * 4; + i += pci_read_base(dev, pci_bar_unknown, res, pos); + if (!res->flags) + continue; + res->flags &= ~IORESOURCE_SIZEALIGN; + res->end = res->start + resource_size(res) * total - 1; + } + + dev->iov = iov; + dev_info(&a...

...BAR: invalid resource #%d\n", resno); + return 0; +} + static void __devinit pci_no_domains(void) { #ifdef CONFIG_PCI_DOMAINS diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 596efa6..9f0fa0e 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -162,5 +162,8 @@ extern int pci_read_base(struct pci_dev *dev, enum pci_bar_type type, struct resource *res, unsigned int reg); extern struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr); +extern int pci_resource_alignment(struct pci...

...BAR: invalid resource #%d\n", resno); + return 0; +} + static void __devinit pci_no_domains(void) { #ifdef CONFIG_PCI_DOMAINS diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 596efa6..9f0fa0e 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -162,5 +162,8 @@ extern int pci_read_base(struct pci_dev *dev, enum pci_bar_type type, struct resource *res, unsigned int reg); extern struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr); +extern int pci_resource_alignment(struct pci...

...GO | S_IWUSR, iov_show, iov_store); + +static int iov_alloc_res(struct pci_dev *pf) +{ + int i; + int reg; + int err; + u64 size; + struct resource *res; + + for (i = 0; i < PCI_IOV_NUM_BAR; i++) { + res = pf->iov->resource + i; + reg = pf->iov->cap + PCI_IOV_BAR_0 + i * 4; + i += pci_read_base(pf, pci_bar_unknown, res, reg); + if (!res->flags) + continue; + + size = resource_size(res) * pf->iov->nr_virtfn; + res->end = res->start + size - 1; + err = pci_bus_alloc_resource(pf->bus, res, size, pf->iov->align, + PCIBIOS_MIN_MEM, + IORESOURCE_P...

...GO | S_IWUSR, iov_show, iov_store); + +static int iov_alloc_res(struct pci_dev *pf) +{ + int i; + int reg; + int err; + u64 size; + struct resource *res; + + for (i = 0; i < PCI_IOV_NUM_BAR; i++) { + res = pf->iov->resource + i; + reg = pf->iov->cap + PCI_IOV_BAR_0 + i * 4; + i += pci_read_base(pf, pci_bar_unknown, res, reg); + if (!res->flags) + continue; + + size = resource_size(res) * pf->iov->nr_virtfn; + res->end = res->start + size - 1; + err = pci_bus_alloc_resource(pf->bus, res, size, pf->iov->align, + PCIBIOS_MIN_MEM, + IORESOURCE_P...

...GO | S_IWUSR, iov_show, iov_store); + +static int iov_alloc_res(struct pci_dev *pf) +{ + int i; + int reg; + int err; + u64 size; + struct resource *res; + + for (i = 0; i < PCI_IOV_NUM_BAR; i++) { + res = pf->iov->resource + i; + reg = pf->iov->cap + PCI_IOV_BAR_0 + i * 4; + i += pci_read_base(pf, pci_bar_unknown, res, reg); + if (!res->flags) + continue; + + size = resource_size(res) * pf->iov->nr_virtfn; + res->end = res->start + size - 1; + err = pci_bus_alloc_resource(pf->bus, res, size, pf->iov->align, + PCIBIOS_MIN_MEM, + IORESOURCE_P...

...be(struct pci_dev *dev, +static int pcie_portdrv_probe(struct pci_dev *dev, const struct pci_device_id *id) { int status; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 3d17641..edc3d12 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -305,7 +305,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) } } -static void __devinit pci_read_bridge_io(struct pci_bus *child) +static void pci_read_bridge_io(struct pci_bus *child) { struct pci_dev *dev = child->self; u8 io_base_lo, io_limit_lo; @@ -345,7 +345,7 @@ static void __devinit pc...

...be(struct pci_dev *dev, +static int pcie_portdrv_probe(struct pci_dev *dev, const struct pci_device_id *id) { int status; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 3d17641..edc3d12 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -305,7 +305,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) } } -static void __devinit pci_read_bridge_io(struct pci_bus *child) +static void pci_read_bridge_io(struct pci_bus *child) { struct pci_dev *dev = child->self; u8 io_base_lo, io_limit_lo; @@ -345,7 +345,7 @@ static void __devinit pc...

...>stride = stride; + iov->align = pgsz << 12; + mutex_init(&iov->mutex); + + for (i = 0; i < PCI_IOV_NUM_BAR; i++) { + res = dev->resource + PCI_IOV_RESOURCES + i; + pos = iov->cap + PCI_IOV_BAR_0 + i * 4; + i += pci_read_base(dev, pci_bar_unknown, res, pos); + if (!res->flags) + continue; + res->end = res->start + (res->end - res->start + 1) * total - 1; + } + + dev->iov = iov; + dev_info(&dev->dev, "SR-IOV capability is in...

...fset; + iov->stride = stride; + iov->align = pgsz << 12; + iov->maxbus = (dev->devfn + offset + stride * (total - 1)) >> 8; + + for (i = 0; i < PCI_IOV_NUM_BAR; i++) { + res = dev->resource + PCI_IOV_RESOURCES + i; + pos = iov->cap + PCI_IOV_BAR_0 + i * 4; + i += pci_read_base(dev, pci_bar_unknown, res, pos); + if (!res->flags) + continue; + res->flags &= ~IORESOURCE_SIZEALIGN; + res->end = res->start + resource_size(res) * total - 1; + } + + dev->iov = iov; + + return 0; +} + +/** + * pci_iov_release - release resources used by SR-IOV capability...