Displaying 6 results from an estimated 6 matches for "pci_nr_functions".
2019 May 16
3
[PATCH 05/10] s390/cio: introduce DMA pools to cio
..._cpu (for the summary bit vector)
The options are:
* page allocations for everything
* dma_pool for AIRQ_IV_CACHELINE ,gen_pool for others
* dma_pool for everything
I think we should do option 3 and use a dma_pool with cachesize
alignment for everything (as a prerequisite we have to limit
config PCI_NR_FUNCTIONS to 2K - but that is not a real constraint).
Sebastian
2019 May 16
3
[PATCH 05/10] s390/cio: introduce DMA pools to cio
..._cpu (for the summary bit vector)
The options are:
* page allocations for everything
* dma_pool for AIRQ_IV_CACHELINE ,gen_pool for others
* dma_pool for everything
I think we should do option 3 and use a dma_pool with cachesize
alignment for everything (as a prerequisite we have to limit
config PCI_NR_FUNCTIONS to 2K - but that is not a real constraint).
Sebastian
2019 May 22
1
[PATCH 05/10] s390/cio: introduce DMA pools to cio
...I prefer this. Explanation follows.
>
> > * dma_pool for everything
> >
>
> Less waste by factor factor 16.
>
> > I think we should do option 3 and use a dma_pool with cachesize
> > alignment for everything (as a prerequisite we have to limit
> > config PCI_NR_FUNCTIONS to 2K - but that is not a real constraint).
>
> I prefer option 3 because it is conceptually the smallest change, and
^
2
> provides the behavior which is closest to the current one.
I can see that this is the smallest change on top of the current
impl...
2019 May 20
0
[PATCH 05/10] s390/cio: introduce DMA pools to cio
...for AIRQ_IV_CACHELINE ,gen_pool for others
I prefer this. Explanation follows.
> * dma_pool for everything
>
Less waste by factor factor 16.
> I think we should do option 3 and use a dma_pool with cachesize
> alignment for everything (as a prerequisite we have to limit
> config PCI_NR_FUNCTIONS to 2K - but that is not a real constraint).
>
I prefer option 3 because it is conceptually the smallest change, and
provides the behavior which is closest to the current one.
Commit 414cbd1e3d14 "s390/airq: provide cacheline aligned
ivs" (Sebastian Ott, 2019-02-27) could have been s...
2019 May 10
3
[PATCH 05/10] s390/cio: introduce DMA pools to cio
On Fri, 10 May 2019 00:11:12 +0200
Halil Pasic <pasic at linux.ibm.com> wrote:
> On Thu, 9 May 2019 12:11:06 +0200
> Cornelia Huck <cohuck at redhat.com> wrote:
>
> > On Wed, 8 May 2019 23:22:10 +0200
> > Halil Pasic <pasic at linux.ibm.com> wrote:
> >
> > > On Wed, 8 May 2019 15:18:10 +0200 (CEST)
> > > Sebastian Ott <sebott
2019 May 10
3
[PATCH 05/10] s390/cio: introduce DMA pools to cio
On Fri, 10 May 2019 00:11:12 +0200
Halil Pasic <pasic at linux.ibm.com> wrote:
> On Thu, 9 May 2019 12:11:06 +0200
> Cornelia Huck <cohuck at redhat.com> wrote:
>
> > On Wed, 8 May 2019 23:22:10 +0200
> > Halil Pasic <pasic at linux.ibm.com> wrote:
> >
> > > On Wed, 8 May 2019 15:18:10 +0200 (CEST)
> > > Sebastian Ott <sebott