search for: p5600

...for non-Linux system). For that reason my patch for lightweight SYNCs has an option - implement it or implement a generic SYNC. It is possible that some vendor did it in different way but nobody knows or test it. But as a minimum - SYNC must be implemented in spinlocks/atomics/bitops, in recent P5600 it is proven that read can pass write in atomics. MIPS R6 is a different story, I verified lightweight SYNCs from the beginning and it also should use SYNCs. - Leonid.

...for non-Linux system). For that reason my patch for lightweight SYNCs has an option - implement it or implement a generic SYNC. It is possible that some vendor did it in different way but nobody knows or test it. But as a minimum - SYNC must be implemented in spinlocks/atomics/bitops, in recent P5600 it is proven that read can pass write in atomics. MIPS R6 is a different story, I verified lightweight SYNCs from the beginning and it also should use SYNCs. - Leonid.

The term "target" is somewhat overloaded. When llvm-config tells you it was built with the X86 target, that actually includes a variety of closely related architectures, such as x86_64, i386, and so on. Within the x86_64 architecture, there are many individual processor implementations that LLVM understands, such as Skylake, Bulldozer, and many many more. What *clang* means by

Hi Andrew, I seem to be making good progress on the P5600 scheduler using the new machine model but I've got a few questions about it. How would you represent an instruction that splits into two micro-ops and is dispatched to two different reservation stations? For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is spl...

...niel Sanders Cc: LLVM Developers Mailing List (llvmdev at cs.uiuc.edu) Subject: Re: New machine model questions On Jan 24, 2014, at 2:21 AM, Daniel Sanders <Daniel.Sanders at imgtec.com<mailto:Daniel.Sanders at imgtec.com>> wrote: Hi Andrew, I seem to be making good progress on the P5600 scheduler using the new machine model but I've got a few questions about it. Hi Daniel, These are really good questions. For future reference, I might provide better examples if you attach what you have so far for the model. How would you represent an instruction that splits into two micro-o...

...stem). For that reason my patch > for lightweight SYNCs has an option - implement it or implement a > generic SYNC. It is possible that some vendor did it in different > way but nobody knows or test it. But as a minimum - SYNC must be > implemented in spinlocks/atomics/bitops, in recent P5600 it is > proven that read can pass write in atomics. > > MIPS R6 is a different story, I verified lightweight SYNCs from the > beginning and it also should use SYNCs. So you need to build a different kernel for some types of MIPS systems? Or do you do boot-time rewriting, like a number...

Hi Daniel,    Thank you your replying.     Yes, the problem is about MIPS backend. You give me this message "There is limited support for the <8 x f16> type when MSA (MIPS SIMD Architecture) is enabled but even then scalar half-precision is not currently supported."  Could you give me some official link or some evidence? Thank you very much. Robin yalong at multicorewareinc.com

...reason my patch >> for lightweight SYNCs has an option - implement it or implement a >> generic SYNC. It is possible that some vendor did it in different >> way but nobody knows or test it. But as a minimum - SYNC must be >> implemented in spinlocks/atomics/bitops, in recent P5600 it is >> proven that read can pass write in atomics. >> >> MIPS R6 is a different story, I verified lightweight SYNCs from the >> beginning and it also should use SYNCs. > So you need to build a different kernel for some types of MIPS systems? > Or do you do boot-time...

...reason my patch >> for lightweight SYNCs has an option - implement it or implement a >> generic SYNC. It is possible that some vendor did it in different >> way but nobody knows or test it. But as a minimum - SYNC must be >> implemented in spinlocks/atomics/bitops, in recent P5600 it is >> proven that read can pass write in atomics. >> >> MIPS R6 is a different story, I verified lightweight SYNCs from the >> beginning and it also should use SYNCs. > So you need to build a different kernel for some types of MIPS systems? > Or do you do boot-time...

On 01/14/2016 01:29 PM, Paul E. McKenney wrote: > >> On 01/14/2016 12:34 PM, Paul E. McKenney wrote: >>> >>> The WRC+addr+addr is OK because data dependencies are not required to be >>> transitive, in other words, they are not required to flow from one CPU to >>> another without the help of an explicit memory barrier. >> I don't see any

On 01/14/2016 01:29 PM, Paul E. McKenney wrote: > >> On 01/14/2016 12:34 PM, Paul E. McKenney wrote: >>> >>> The WRC+addr+addr is OK because data dependencies are not required to be >>> transitive, in other words, they are not required to flow from one CPU to >>> another without the help of an explicit memory barrier. >> I don't see any

...g/lib/Basic/Targets/Mips.cpp". mips1 and mips5 accepted by Clang, but unsupported by code generator. I'm going to remove them from this list. mips1, mips2, mips3, mips4, mips5, mips32, mips32r2, mips32r3, mips32r5, mips32r6, mips64, mips64r2, mips64r3, mips64r5, mips64r6, octeon, octeon+, p5600 R3000 is a CPU implements mips1 instruction set architecture. Unfortunately you cannot generate a code for this CPU using Clang. -- Simon Atanasyan Als GmbH eingetragen im Handelsregister Bad Homburg v.d.H. HRB 9816, USt.ID-Nr. DE 114 165 789 Geschäftsführer: Dr. Hiroshi Nakamura, Dr. Robert Plan...

...little endian, obviously" but this is not actually correct all the time. The true answer is 'whatever I (the person who built the toolchain) want it to mean'. It could be mips32r6, it could be mips4, it could even be big-endian mips64r5 with nan2008 and msa. It could even be octeon or p5600. In GCC toolchains, distributors routinely use configure-time options to define the triple they wish to use. Nothing is stopping anyone using the same string for completely different meanings and indeed conflicting definitions are very common. To be compatible with GCC toolchains we must be able to...

I think we need to take a step further back and re-enter from the right starting point. The thing that's bothering me about the push back so far is that it's trying to discuss and understand the consequences of resolving the core problem while seemingly ignoring the core problem itself. The reason I've been steering everything back to GNU Triple's being ambiguous and inconsistent