search for: p32

...asier to write the target in the style of the C-backend (which > doesn't use any of the code generator components). If it does, making > use of the code generator infrastructure would make sense. > > -Chris > Sample from SUIF disassembler (done by someone else): lda $vr10.p32 <- main.A cvt $vr11.p32 <- $vr10.p32 add $vr12.p32 <- $vr11.p32,$vr9.s32 lod $vr13.s32 <- 0($vr12.p32) cvt $vr8.s32 <- $vr13.s32 mul $vr6.s32 <- $vr7.s32,$vr8.s32 ldc $vr15.s32 <- 5 ldc $vr18.s32 <- 1 add $vr17.s32 <- main.i,$vr18.s32 ******************** So I gu...

On Tue, 18 Jan 2005, John Cortes wrote: >> Can you say a little bit about MACH-SUIF? With a brief google search, I >> didn't turn up anything that described the architecture. Is it a RISC-like >> machine with 32-bit instruction words? >> > > It's another VM representation. I haven't really gotten to know the nitty > gritty of the language so

Quentin, My real problem is that my target has separate address and data registers. The way I’d like to try getting better reg-alloc than I am now is to bring out the difference as Early as possible, so I have added p16, p32, p64 to the enum in “MachineValueType.h” And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass); And I have an override for virtual TargetLowering::getPointerTy() that returns MVT::p32, And some other minor changes that altogether cause virt-regs that contain pointers To get...

...;llvm-dev at lists.llvm.org> wrote: > > Quentin, > My real problem is that my target has separate address and data registers. > The way I’d like to try getting better reg-alloc than I am now is to bring out the difference as > Early as possible, so I have added p16, p32, p64 to the enum in “MachineValueType.h” > > And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass); > > And I have an override for virtual TargetLowering::getPointerTy() that returns MVT::p32, > > And some other minor changes that altogether cause virt-...

...at lists.llvm.org> wrote: > > Quentin, > My real problem is that my target has separate address and > data registers. > The way I’d like to try getting better reg-alloc than I am now is to bring > out the difference as > Early as possible, so I have added p16, p32, p64 to the enum in > “MachineValueType.h” > > And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass); > > And I have an override for virtual TargetLowering::getPointerTy() that > returns MVT::p32, > > And some other minor changes that altogether cause v...

...2_create_buffers32 { @@ -257,8 +254,7 @@ struct v4l2_create_buffers32 { __u32 memory; /* enum v4l2_memory */ struct v4l2_format32 format; __u32 capabilities; - __u32 flags; - __u32 reserved[6]; + __u32 reserved[7]; }; static int __bufsize_v4l2_format(struct v4l2_format32 __user *p32, u32 *size) @@ -359,8 +355,7 @@ static int get_v4l2_create32(struct v4l2_create_buffers __user *p64, { if (!access_ok(p32, sizeof(*p32)) || copy_in_user(p64, p32, - offsetof(struct v4l2_create_buffers32, format)) || - assign_in_user(&p64->flags, &p32->flags)) + offs...

...0.082 0.093 0.141 ano$cxxcXI 513851 716.83 -0.125 0.081 0.035 -0.036 -0.050 0.048 0.054 0.061 0.093 0.023 ano$cxxcXII 802332 895.73 -0.658 0.427 0.184 -0.190 -0.264 0.254 0.285 0.323 0.491 0.124 0.082 ano$cxx (Intercept) 251374 501.37 ano$p32 12140 110.18 -0.866 ano$p33 48679 220.63 -0.874 0.757 Residual 150767 388.29 Number of obs: 2238, groups: ano$id, 254; ano$cxx, 12 Fixed effects: Estimate Std. Error t value (Intercept) 76748.8 312.9 245.28 ano$p32 -1343.0 40...

...h> +#include <asm/hypervisor.h> +#include <asm/uaccess.h> +#include <xen/public/privcmd.h> + +int privcmd_ioctl_32(int fd, unsigned int cmd, unsigned long arg) +{ + int ret; + + switch (cmd) { + case IOCTL_PRIVCMD_MMAP_32: { + struct privcmd_mmap *p; + struct privcmd_mmap_32 *p32; + struct privcmd_mmap_32 n32; + + p32 = compat_ptr(arg); + p = compat_alloc_user_space(sizeof(*p)); + if (copy_from_user(&n32, p32, sizeof(n32)) || + put_user(n32.num, &p->num) || + put_user(n32.dom, &p->dom) || + put_user(compat_ptr(n32.entry), &p->entr...

...-27 20:36:59.189424147 +0100 @@ -2765,6 +2765,26 @@ static void compat_ioctl_error(struct fi free_page((unsigned long)path); } +#ifdef BROKEN_X86_ALIGNMENT +/* just account for different alignment */ +static unsigned long copy_to_space_resv(unsigned long arg) +{ + struct space_resv_32 __user *p32 = (void __user *)arg; + struct space_resv __user *p = compat_alloc_user_space(sizeof(*p)); + + if (copy_in_user(&p->l_type, &p32->l_type, sizeof(s16)) || + copy_in_user(&p->l_whence, &p32->l_whence, sizeof(s16)) || + copy_in_user(&p->l_start, &p32-&gt...

...ts.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Quentin, My real problem is that my target has separate address and data registers. The way I’d like to try getting better reg-alloc than I am now is to bring out the difference as Early as possible, so I have added p16, p32, p64 to the enum in “MachineValueType.h” And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass); And I have an override for virtual TargetLowering::getPointerTy() that returns MVT::p32, And some other minor changes that altogether cause virt-regs that contain pointers To get...

...ote: > > > > Quentin, > > My real problem is that my target has separate address and > data registers. > > The way I’d like to try getting better reg-alloc than I am now is to bring > out the difference as > > Early as possible, so I have added p16, p32, p64 to the enum in > “MachineValueType.h” > > > > And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass); > > > > And I have an override for virtual TargetLowering::getPointerTy() that > returns MVT::p32, > > > > And some other minor c...

Hi all, this patch series introduces stolen ticks accounting for Xen on ARM. Stolen ticks are clocksource ticks that have been "stolen" from the cpu, typically because Linux is running in a virtual machine and the vcpu has been descheduled. To account for these ticks we introduce CONFIG_PARAVIRT and pv_time_ops so that we can make use of:

Hi Peter, I would recommend looking into the implementation of the matcher if you want to add more builtin types: utils/TableGen//DAGISelMatcherGen.cpp That being said, you can define your own types without having to go through that hassle. E.g., from AArch64 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> { let ParserMatchClass =

Dumb question about llvm-tblgen for "XyzGenInstrInfo.inc" If I have a pattern in my dot-td-file like this [(set i32:$dst (add i32:$rs1, i32:$rs2))] The question is where does the token "i32" come from, I don't see any definitions for i1, i8, i16, i32, ... in include/llvm/Target/*.td while I do see definitions for tokens like

Hi everyone, I'm looking through codes related to registered pressure tracking, mainly the source files 'RegisterPressure.h/cpp', 'MachineRegisterInfo.h/cpp', 'TargetRegisterInfo.h/cpp'. There is a concept I can hardly understand, the 'register pressure set'. Class 'TargetRegisterInfo' defines two virtual methods 'getRegClassPressureSets' and

...try the following code: huang.cor <- readMoments(diag=FALSE, names=c('x1', 'x2', 'x3', 'y')) 0.76 0.91 0.72 0.94 0.77 0.83 huang.mod <- specifyModel() x1 -> y, p1 x2 -> y, p2 x3 -> y, p3 x1 -> x2, p12 x2 -> x1, p21 x2 -> x3, p23 x3 -> x2, p32 x1 -> x3, p13 x3 -> x1, p31 huang.sem <- sem(huang.mod, huang.cor, 100)# 100 is arbitarious. It give the error message: Error in sem.default(ram, S = S, N = N, raw = raw, data = data, param.names = pars, : The model has negative degrees of freedom = -3 I don't know why. I hop...

...4) p8=g(-5,5) p9=g(-4,-.5) p10=g(-4,0) p11=g(-4,0.5) p12=g(-4,1) p13=g(-4,2) p14=g(-4,3) p15=g(-4,4) p16=g(-4,5) p17=g(-3,-.5) p18=g(-3,0) p19=g(-3,.5) p20=g(-3,1) p21=g(-3,2) p22=g(-3,3) p23=g(-3,4) p24=g(-3,5) p25=g(-2,-.5) p26=g(-2,0) p27=g(-2,.5) p28=g(-2,1) p29=g(-2,2) p30=g(-2,3) p31=g(-2,4) p32=g(-2,5) p33=g(-1,-.5) p34=g(-1,0) p35=g(-1,.5) p36=g(-1,1) p37=g(-1,2) p38=g(-1,3) p39=g(-1,4) p40=g(-1,5) p41=g(-0.5,-0.5) p42=g(-0.5,0) p43=g(-0.5,0.5) p44=g(-0.5,1) p45=g(-0.5,2) p46=g(-0.5,3) p47=g(-0.5,4) p48=g(-0.5,5) p49=g(0,-0.5) p50=g(0,0) p51=g(0,.5) p52=g(0,1) p53=g(0,2) p54=g(0,3) p55=g...

...g to get access to a userland string that''s behind a second level pointer using DTrace, but I can''t seem to get it to work. I started with the example on the Team DTrace Tips and Tricks slides: trace(copyinstr(*(uintptr_t *)copyin(arg0, curpsinfo->pr_dmodel == PR_MODEL_ILP32 ? 4 : 8))); And when I couldn''t get it to work, I started breaking it down into smaller pieces to see what was going on at each step. Here''s the "C" and "D" code: --- pt.c --- static int sz = sizeof(char *); main() { char *s = "abcdefghijk";...

Dear Rxperts, I have a varaibles data file that looks like this p(1) 10 p(1) 3 p(1) 4 p(2) 20 p(2) 30 p(2) 40 p(3) 4 p(3) 1 p(1) 2 I cannot process these data with R because it does not like the parentheses. How can I get these to look like: p1 10 p1 3 p1 4 p2 20 p2 30 p2 40 p3 4 p3 1 p3 2 The data is in a tab delimited text file and I want to get it into a data.frame(). Many thanks in

...uld be right. > > The behaviour of the code generator for big-endian NEON and MIPS is > derived from the fact that we did not want to change IR semantics at > all. A fundamental property that we do not want to break is memory > round-tripping: > > %1 = load <4 x i32>, %p32 > %2 = bitcast <4 x i32> %1 to <2 x i64> > store <2 x i64> %2, (bitcast %p32 to <2 x i64>*) > > The value of memory before and after the store MUST NOT change > (contrary to what I said in an earlier post, I know). > > So in fact everything you can do i...