Displaying 20 results from an estimated 141 matches for "p15".
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2012 Feb 13
0
[PATCH 10/14] arm: implement ARMv7 tlb ops.
...flush_cache_all)
stmfd sp!, {r4-r5, r7, r9-r11, lr}
v7_way_op c14
@@ -59,9 +58,7 @@ PRIVATE(v7_flush_cache_all)
ldmfd sp!, {r4-r5, r7, r9-r11, lr}
mov pc, lr
-DECLARE_CPU_OP(cpu_flush_cache_all, v7_flush_cache_all)
-
-PRIVATE(v7_flush_cache_range)
+ENTRY(cpu_flush_cache_range)
mrc p15, 1, r3, c0, c0, 0 @ read CSIDR
and r3, r3, #7 @ cache line size encoding
mov r3, #16 @ size offset
@@ -74,9 +71,7 @@ 1:
dsb
mov pc, lr
-DECLARE_CPU_OP(cpu_flush_cache_range, v7_flush_cache_range)
-
-PRIVATE(v7_clean_cache_range)
+ENTRY(cpu_clean_cache_range)
mrc p15, 1, r...
2008 May 28
0
ia64/pv_ops: preparation: move some functions in ivt.S to avoid lack of space.
...n r31, psr.dt may be off, r16 is faulting address)
-ENTRY(page_fault)
- SSM_PSR_DT_AND_SRLZ_I
- ;;
- SAVE_MIN_WITH_COVER
- alloc r15=ar.pfs,0,0,3,0
- MOV_FROM_IFA(out0)
- MOV_FROM_ISR(out1)
- SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(r14, r3)
- adds r3=8,r2 // set up second base pointer
- SSM_PSR_I(p15, p15, r14) // restore psr.i
- movl r14=ia64_leave_kernel
- ;;
- SAVE_REST
- mov rp=r14
- ;;
- adds out2=16,r12 // out2 = pointer to pt_regs
- br.call.sptk.many b6=ia64_do_page_fault // ignore return address
-END(page_fault)
-
.org ia64_ivt+0x1c00
//////////////////////////////////////////////...
2008 May 28
0
ia64/pv_ops: preparation: move some functions in ivt.S to avoid lack of space.
...n r31, psr.dt may be off, r16 is faulting address)
-ENTRY(page_fault)
- SSM_PSR_DT_AND_SRLZ_I
- ;;
- SAVE_MIN_WITH_COVER
- alloc r15=ar.pfs,0,0,3,0
- MOV_FROM_IFA(out0)
- MOV_FROM_ISR(out1)
- SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(r14, r3)
- adds r3=8,r2 // set up second base pointer
- SSM_PSR_I(p15, p15, r14) // restore psr.i
- movl r14=ia64_leave_kernel
- ;;
- SAVE_REST
- mov rp=r14
- ;;
- adds out2=16,r12 // out2 = pointer to pt_regs
- br.call.sptk.many b6=ia64_do_page_fault // ignore return address
-END(page_fault)
-
.org ia64_ivt+0x1c00
//////////////////////////////////////////////...
2013 Feb 18
3
foreach loop, stata equivalent
Hi! I'm a recent convert from Stata, so forgive my ignorance.
In Stata, I can write foreach loops (example below)
foreach var of varlist p1-p14 {
foreach y of varlist p15-p269 {
reg `var' `y'
}
}
It's looping p1-p15, p1-p16...., p1-p269, p2-p15, p2-p16,... p2-p269,...
variable pairs.
How can I write something similar in R?
I 'tried' understanding the package.foreach but can't get it to work.
Thanks for any help
Nelissa...
2012 Feb 13
0
[PATCH 05/14] arm: implement exception and hypercall entries.
..., sp, #CTXT_FRAME_SIZE
+SPFIX( tst sp, #4 )
+SPFIX( bicne sp, sp, #4 )
+ stmib sp, {r1 - lr}^
+ ldmia r0, {r1 - r3}
+ add r5, sp, #CTXT_SSP
+ add r0, sp, #CTXT_FRAME_SIZE
+SPFIX( addne r0, r0, #4 )
+ str r1, [sp]
+ mov r1, lr
+ stmia r5, {r0 - r3}
+
+ mrc p15, 0, r0, c6, c0, 0
+ mrc p15, 0, r1, c5, c0, 0
+
+ and r4, r3, #PSR_MODE_MASK
+ eors r4, r4, #PSR_MODE_SVC
+
+ beq do_data_abort
+
+ cpsie i
+
+ cci r8
+ ldr r9, [r8]
+
+ ldr r10, [r9, #OFFSET_VCPU_INFO ]
+ ldr r14, [r9, #(OFFSET_ARCH_VCPU + OFFSET_GUEST_CONTEXT + OFFSET_VCPU_V...
2002 Oct 22
1
constraints again
...ng function on my data.
out.nls<-nls(z ~ p1+
(p2*dat)+(p3*dat^2)+(p4*dat^3)+(p5*AgeS)+(p6*AgeS^2)+(p7*AgeS^3)+
(p8*(dat*AgeS))+(p9*(dat^2*AgeS))+(p10*(dat^3*AgeS))+
(p11*(dat*AgeS^2))+(p12*(dat*AgeS^3))+(p13*(dat^2*AgeS^2))+
(p14*(dat^2*AgeS^3))+(p15*(dat^3*AgeS^3)),
start=list(p1=0,p2=0,p3=0,p4=0,p5=0,p6=0,p7=0,p8=0,p9=0,p10=0,p11=0,p12=0,p1
3=0,p14=0,p15=0),trace=trace,
control=control)
which relates the z-score on a IQ subtest to Age (AgeS) and Raw Score (dat).
Allthough the dataset is quite large, older subjects usually do not pr...
2013 Feb 20
1
[LLVMdev] Question about accessing coprocesser register in prologue
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2012 Sep 18
2
[LLVMdev] liveness assertion problem in llc
...t from that, I have no clue...
Here is the end of a log I get under gdb (gdb used for getting a more informative backtrace):
# *** IR Dump Before Calculate spill weights ***:
# Machine code for function CGA_kernel_read: Post SSA
Function Live Ins: %P0 in %vreg5, %P1 in %vreg6
Function Live Outs: %P15
0B BB#0: derived from LLVM BB %entry
Live Ins: %P0 %P1
16B %vreg6<def> = COPY %P1; IntRegs:%vreg6
48B %vreg8<def> = MOV32ri <ga:@fifo>, pred:%noreg; IntRegs:%vreg8 dbg:../src/getbits.c:46:1
64B %vreg9<def> = LDUBri %vreg8, 1, pred:%noreg; mem:LD1[getelementptr inbou...
2009 Apr 04
1
Problem with sample()
...0148319138404727000000
p7 = B * 0.0122476323793264000000
p8 = B * 0.0102907015781317000000
p9 = B * 0.0087621664064845000000
p10 = B * 0.0075394959058307200000
p11 = B * 0.0065429288357371100000
p12 = B * 0.0057182186634501300000
p13 = B * 0.0050271368777644200000
p14 = B * 0.0044419396829380100000
p15 = B * 0.0039419891495863900000
p16 = B * 0.0035116072275277300000
p17 = B * 0.0031386664156453200000
p18 = B * 0.0028136371529372800000
p19 = B * 0.0025289275577435600000
p20 = B * 0.0022784155915110200000
p21 = B * 0.0020571110286774600000
p22 = B * 0.0018609069242876300000
p23 = B * 0.00168639400...
2008 Feb 25
6
[PATCH 0/4] ia64/xen: paravirtualization of hand written assembly code
Hi. The patch I send before was too large so that it was dropped from
the maling list. I'm sending again with smaller size.
This patch set is the xen paravirtualization of hand written assenbly
code. And I expect that much clean up is necessary before merge.
We really need the feed back before starting actual clean up as Eddie
already said before.
Eddie discussed how to clean up and suggested
2008 Feb 25
6
[PATCH 0/4] ia64/xen: paravirtualization of hand written assembly code
Hi. The patch I send before was too large so that it was dropped from
the maling list. I'm sending again with smaller size.
This patch set is the xen paravirtualization of hand written assenbly
code. And I expect that much clean up is necessary before merge.
We really need the feed back before starting actual clean up as Eddie
already said before.
Eddie discussed how to clean up and suggested
2012 Sep 18
0
[LLVMdev] liveness assertion problem in llc
On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote:
> I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some
2012 Apr 26
0
[LLVMdev] Trouble with tweaking test-release.sh script
...: CXX/conv/conv.prom/p2.cpp
chandlerc doubts the test itself is fulfill the C++ standard. Although
"-fshort-wchar" makes the error disappered, chandlerc think it's not
the correct solution. Perhaps it's test bug not clang's.
Clang :: CXX/special/class.copy/p15-inclass.cpp
Clang :: CodeGenCXX/compound-literals.cpp
Clang :: CodeGenCXX/copy-constructor-elim-2.cpp
Clang :: CodeGenCXX/cxx0x-initializer-references.cpp
Clang :: CodeGenCXX/cxx0x-initializer-stdinitializerlist-startend.cpp
Clang :: CodeGenCXX/virt-call-offsets.cpp
Clang ::...
2012 Apr 26
2
[LLVMdev] Trouble with tweaking test-release.sh script
On Apr 24, 2012, at 8:05 PM, 陳韋任 wrote:
> Hi Bill,
>
> I forgot to do Phase2/Phase3 build. Here is the Phase3 regression test
> result,
>
> http://people.cs.nctu.edu.tw/~chenwj/tmp/phase3-regression-test.txt
>
> Most LLVM failures are gone. As for ExecutionEngine, I guess ARM JIT is
> not at a good shape at this moment, right? Perhaps we should focus on Clang
>
2008 Mar 28
0
[08/17][PATCH] kvm/ia64: Add interruption vector table for vmm.
Hi, Xiantao
a comments is below.
>+// 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
>+ENTRY(kvm_interrupt)
>+ mov r31=pr // prepare to save predicates
>+ mov r19=12
>+ mov r29=cr.ipsr
>+ ;;
>+ tbit.z p6,p7=r29,IA64_PSR_VM_BIT
>+ tbit.z p0,p15=r29,IA64_PSR_I_BIT
>+ ;;
>+(p7) br.sptk kvm_dispatch_interrupt
>+ ;;
>+ mov r27=ar.rsc /* M */
>+ mov r20=r1 /* A */
>+ mov r25=ar.unat /* M */
>+ mov r26=ar.pfs /* I */
>+ mov r28=cr.iip /* M */
>+ cover /* B (or nothing) */
>+ ;;
&g...
2008 Mar 28
0
[08/17][PATCH] kvm/ia64: Add interruption vector table for vmm.
Hi, Xiantao
a comments is below.
>+// 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
>+ENTRY(kvm_interrupt)
>+ mov r31=pr // prepare to save predicates
>+ mov r19=12
>+ mov r29=cr.ipsr
>+ ;;
>+ tbit.z p6,p7=r29,IA64_PSR_VM_BIT
>+ tbit.z p0,p15=r29,IA64_PSR_I_BIT
>+ ;;
>+(p7) br.sptk kvm_dispatch_interrupt
>+ ;;
>+ mov r27=ar.rsc /* M */
>+ mov r20=r1 /* A */
>+ mov r25=ar.unat /* M */
>+ mov r26=ar.pfs /* I */
>+ mov r28=cr.iip /* M */
>+ cover /* B (or nothing) */
>+ ;;
&g...
2006 Aug 18
1
dovecot vs qpopper performance testing results
...connections,IMAP connections
Results (only the best one shown):
Qpopper:
1 parallel processes:
12:36,1020,111470,0,6,0,0
5 parallel clients:
12:44,3246,366207,0,13,0,0
15 parallel clients:
13:06,4099,481347,0,48,0,0
Dovecot:
p1:
12:19,3316,367859,0,13,0,0
p5:
12:50,4653,524456,0,34,0,0
p15:
12:56,5063,578889,0,84,0,0
As you can see, Dovecot is faster.. With 15 parallel processes it seems
to have saturated my 100Mbit/s LAN (578889 kB data in one minute).
Dovecot had noticeably smaller disk IO and system load was smaller too,
probably thanks to smaller IO.
Qpopper performed bet...
2008 Oct 22
1
Spatstat help - quadratcount query
Hi all,
I am using quadratcount in spatstat to divide a window containing a
point pattern into a grid of quadrats containing the intensity of points
in each quadrat. My data is in UTM co-ordinates. My window is defined
as follows:
>p15<-ppp(x,y,window=owin(c(341710,342100),c(3126465,3126780)),marks=NUL
L, checks=TRUE)
Giving me a distance of 390m in the 'x' direction and 315m in the 'y'
direction. I want to divide the window into quadrats of size 15m x 15m
so I did the following:
>q15<-quadratcount(p15...
2008 May 19
18
[PATCH 00/17] ia64/pv_ops take 6
Hi. This patchset implements ia64/pv_ops support which is the
framework for virtualization support.
Changes from take 5 are rebased to Linux 2.6.26-rc3,
bug fix ivt.S paravirtualization and multi entry point support.
I believe these patches can be applied to the linux ia64 repository.
On x86 various ways to support virtualization were proposed, and
eventually pv_ops won. So on ia64 the pv_ops
2008 May 19
18
[PATCH 00/17] ia64/pv_ops take 6
Hi. This patchset implements ia64/pv_ops support which is the
framework for virtualization support.
Changes from take 5 are rebased to Linux 2.6.26-rc3,
bug fix ivt.S paravirtualization and multi entry point support.
I believe these patches can be applied to the linux ia64 repository.
On x86 various ways to support virtualization were proposed, and
eventually pv_ops won. So on ia64 the pv_ops