Displaying 20 results from an estimated 24 matches for "orq".
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2008 Dec 22
3
Convert ASCII string to Decimal in R (vice versa) was: Hex
Hi Dieter,
Sorry my mistake. I wanted to convert them
into Decimal (not Hexadecimal).
Given this string, the desired answer follows:
> ascii_str <- "ORQ>IK"
79 82 81 62 73 75
> ascii_str2 <- "FDC"
70 68 67
- Gundala Viswanath
Jakarta - Indonesia
On Mon, Dec 22, 2008 at 5:49 PM, Dieter Menne
<dieter.menne at menne-biomed.de> wrote:
> Gundala Viswanath <gundalav <at> gmail.com> writes:
>
>> F...
2017 Sep 19
0
How to add optimizations to InstCombine correctly?
...tions from
Chad. However, running the lit checks for the x86 backend I observe some
changes in the generated MC, e.g.:
llvm/test/CodeGen/X86/lea-3.ll:13:10: error: expected string not found
in input
; CHECK: leal ([[A0]],[[A0]],2), %eax
^
<stdin>:10:2: note: scanning from here
orq %rdi, %rax
^
<stdin>:10:2: note: with variable "A0" equal to "%rdi"
orq %rdi, %rax
^
<stdin>:10:2: note: with variable "A0" equal to "%rdi"
orq %rdi, %rax
^
<stdin>:23:2: note: possible intended match here
leal (,%rdi,4), %eax...
2017 Sep 16
2
How to add optimizations to InstCombine correctly?
This conversation has (partially) moved on to D37896 now, but if possible I was hoping that we could perform this in DAGCombiner and remove the various target specific combines that we still have.
At least ARM/AARCH64 and X86 have cases that can hopefully be generalised and removed, but there will probably be a few legality/perf issues that will occur.
Simon.
> On 14 Sep 2017, at 06:23,
2017 Sep 19
0
How to add optimizations to InstCombine correctly?
...gestions from
Chad. However, running the lit checks for the x86 backend I observe some
changes in the generated MC, e.g.:
llvm/test/CodeGen/X86/lea-3.ll:13:10: error: expected string not found
in input
; CHECK: leal ([[A0]],[[A0]],2), %eax
^
<stdin>:10:2: note: scanning from here
orq %rdi, %rax
^
<stdin>:10:2: note: with variable "A0" equal to "%rdi"
orq %rdi, %rax
^
<stdin>:10:2: note: with variable "A0" equal to "%rdi"
orq %rdi, %rax
^
<stdin>:23:2: note: possible intended match here
leal (,%rdi,4), %eax...
2017 Sep 19
5
How to add optimizations to InstCombine correctly?
...e lit checks for the x86 backend I observe some
> changes in the generated MC, e.g.:
>
> llvm/test/CodeGen/X86/lea-3.ll:13:10: error: expected string not found
> in input
> ; CHECK: leal ([[A0]],[[A0]],2), %eax
> ^
> <stdin>:10:2: note: scanning from here
> orq %rdi, %rax
> ^
> <stdin>:10:2: note: with variable "A0" equal to "%rdi"
> orq %rdi, %rax
> ^
> <stdin>:10:2: note: with variable "A0" equal to "%rdi"
> orq %rdi, %rax
> ^
> <stdin>:23:2: note: possible inten...
2018 Mar 23
5
RFC: Speculative Load Hardening (a Spectre variant #1 mitigation)
...n these examples to hold the special value of `-1` which will be `cmov`ed
over
`%rax` in mis-speculated paths.
Single register addressing mode:
```
...
.LBB0_4: # %danger
cmovneq %r8, %rax # Conditionally update predicate
state.
orq %rax, %rsi # Mask the pointer if
misspeculating.
movl (%rsi), %edi
```
Two register addressing mode:
```
...
.LBB0_4: # %danger
cmovneq %r8, %rax # Conditionally update predicate
state.
orq %rax,...
2016 Jun 29
2
avx512 JIT backend generates wrong code on <4 x float>
...%rdx, %rax
sarq $63, %rax
shrq $62, %rax
addq %rdx, %rax
sarq $2, %rax
movq %r8, %rcx
sarq $63, %rcx
shrq $62, %rcx
addq %r8, %rcx
sarq $2, %rcx
movq %rax, %rdx
shlq $5, %rdx
leaq 16(%r9,%rdx), %rsi
orq $16, %rdx
movq 16(%rsp), %rdi
addq %rdx, %rdi
addq 8(%rsp), %rdx
.align 16, 0x90
.LBB0_1:
vmovaps -16(%rdx), %xmm0
vmovaps (%rdx), %xmm1
vmovaps -16(%rdi), %xmm2
vmovaps (%rdi), %xmm3
vmulps %xmm3, %xmm1, %xmm4
vmulps...
2016 Jun 29
0
avx512 JIT backend generates wrong code on <4 x float>
...x
> addq %rdx, %rax
> sarq $2, %rax
> movq %r8, %rcx
> sarq $63, %rcx
> shrq $62, %rcx
> addq %r8, %rcx
> sarq $2, %rcx
> movq %rax, %rdx
> shlq $5, %rdx
> leaq 16(%r9,%rdx), %rsi
> orq $16, %rdx
> movq 16(%rsp), %rdi
> addq %rdx, %rdi
> addq 8(%rsp), %rdx
> .align 16, 0x90
> .LBB0_1:
> vmovaps -16(%rdx), %xmm0
> vmovaps (%rdx), %xmm1
> vmovaps -16(%rdi), %xmm2
> vmovaps (%rdi), %xmm3
>...
2016 Jun 30
1
avx512 JIT backend generates wrong code on <4 x float>
...$2, %rax
>> movq %r8, %rcx
>> sarq $63, %rcx
>> shrq $62, %rcx
>> addq %r8, %rcx
>> sarq $2, %rcx
>> movq %rax, %rdx
>> shlq $5, %rdx
>> leaq 16(%r9,%rdx), %rsi
>> orq $16, %rdx
>> movq 16(%rsp), %rdi
>> addq %rdx, %rdi
>> addq 8(%rsp), %rdx
>> .align 16, 0x90
>> .LBB0_1:
>> vmovaps -16(%rdx), %xmm0
>> vmovaps (%rdx), %xmm1
>> vmovaps -16(%rdi), %xmm2...
2006 Jun 26
0
[klibc 37/43] x86_64 support for klibc
...+ .align 4
+ .globl __syscall_common
+ .type __syscall_common, at function
+__syscall_common:
+ movq %rcx,%r10 # The kernel uses %r10 istf %rcx
+ syscall
+
+ cmpq $-4095,%rax
+ jnb 1f
+ ret
+
+ # Error return, must set errno
+1:
+ negl %eax
+ movl %eax,errno(%rip) # errno is type int, so 32 bits
+ orq $-1,%rax # orq $-1 smaller than movq $-1
+ ret
+
+ .size __syscall_common,.-__syscall_common
diff --git a/usr/klibc/arch/x86_64/sysstub.ph b/usr/klibc/arch/x86_64/sysstub.ph
new file mode 100644
index 0000000..e2d797b
--- /dev/null
+++ b/usr/klibc/arch/x86_64/sysstub.ph
@@ -0,0 +1,23 @@
+# -*- per...
2007 Apr 18
0
[RFC/PATCH PV_OPS X86_64 03/17] paravirt_ops - system routines
...B enable and PPro Global page
- * enable), so that any CPU's that boot up
- * after us can get the correct flags.
- */
-extern unsigned long mmu_cr4_features;
-
-static inline void set_in_cr4 (unsigned long mask)
-{
- mmu_cr4_features |= mask;
- __asm__("movq %%cr4,%%rax\n\t"
- "orq %0,%%rax\n\t"
- "movq %%rax,%%cr4\n"
- : : "irg" (mask)
- :"ax");
-}
-
-static inline void clear_in_cr4 (unsigned long mask)
-{
- mmu_cr4_features &= ~mask;
- __asm__("movq %%cr4,%%rax\n\t"
- "andq %0,%%rax\n\t"
- "movq %%rax,%%cr...
2007 Apr 18
0
[RFC/PATCH PV_OPS X86_64 03/17] paravirt_ops - system routines
...B enable and PPro Global page
- * enable), so that any CPU's that boot up
- * after us can get the correct flags.
- */
-extern unsigned long mmu_cr4_features;
-
-static inline void set_in_cr4 (unsigned long mask)
-{
- mmu_cr4_features |= mask;
- __asm__("movq %%cr4,%%rax\n\t"
- "orq %0,%%rax\n\t"
- "movq %%rax,%%cr4\n"
- : : "irg" (mask)
- :"ax");
-}
-
-static inline void clear_in_cr4 (unsigned long mask)
-{
- mmu_cr4_features &= ~mask;
- __asm__("movq %%cr4,%%rax\n\t"
- "andq %0,%%rax\n\t"
- "movq %%rax,%%cr...
2013 Mar 06
6
dovecot 2 in ubuntu 12.04 or Debian Squeeze
Dear sir,
I have to set up a mail gateway which will be explored to Internet and a
secure mail server in the Intranet.
I need a smart imap proxy in the mail gateway which will fetch the mail from
server and present to user through either a stand alone mail client or a web
mail client.
All authentication is through ldap server.
I have installed Dovecot 2.2 Unstable in my Ubuntu 12.04 with ssl
2012 Nov 20
12
[PATCH v2 00/11] xen: Initial kexec/kdump implementation
Hi,
This set of patches contains initial kexec/kdump implementation for Xen v2
(previous version were posted to few people by mistake; sorry for that).
Currently only dom0 is supported, however, almost all infrustructure
required for domU support is ready.
Jan Beulich suggested to merge Xen x86 assembler code with baremetal x86 code.
This could simplify and reduce a bit size of kernel code.
2012 Nov 20
12
[PATCH v2 00/11] xen: Initial kexec/kdump implementation
Hi,
This set of patches contains initial kexec/kdump implementation for Xen v2
(previous version were posted to few people by mistake; sorry for that).
Currently only dom0 is supported, however, almost all infrustructure
required for domU support is ready.
Jan Beulich suggested to merge Xen x86 assembler code with baremetal x86 code.
This could simplify and reduce a bit size of kernel code.
2012 Nov 20
12
[PATCH v2 00/11] xen: Initial kexec/kdump implementation
Hi,
This set of patches contains initial kexec/kdump implementation for Xen v2
(previous version were posted to few people by mistake; sorry for that).
Currently only dom0 is supported, however, almost all infrustructure
required for domU support is ready.
Jan Beulich suggested to merge Xen x86 assembler code with baremetal x86 code.
This could simplify and reduce a bit size of kernel code.
2007 Jun 27
0
[PATCH 1/10] Provide basic Xen PM infrastructure
...%r##x
+#define SAVED_GREG(x) saved_r##x(%rip)
+#define DECLARE_GREG(x) saved_r##x: .quad 0
+#define SAVE_GREG(x) movq GREG(x), SAVED_GREG(x)
+#define LOAD_GREG(x) movq SAVED_GREG(x), GREG(x)
+
+#define REF(x) x(%rip)
+
+#define RDMSR(ind, m) \
+ xorq %rdx, %rdx; \
+ mov $ind, %ecx; \
+ rdmsr; \
+ shlq $0x20, %rdx; \
+ orq %rax, %rdx; \
+ movq %rdx, m(%rip);
+
+#define WRMSR(ind, m) \
+ mov $i...
2007 Aug 15
13
[PATCH 0/25][V3] pvops_64 last round (hopefully)
This is hopefully the last iteration of the pvops64 patch.
>From the last version, we have only one change, which is include/asm-x86_64/processor.h: There were still one survivor in raw asm.
Also, git screwed me up for some reason, and the 25th patch was missing the new files, paravirt.{c,h}. (although I do remember having git-add'ed it, but who knows...)
Andrew, could you please push it
2007 Aug 15
13
[PATCH 0/25][V3] pvops_64 last round (hopefully)
This is hopefully the last iteration of the pvops64 patch.
>From the last version, we have only one change, which is include/asm-x86_64/processor.h: There were still one survivor in raw asm.
Also, git screwed me up for some reason, and the 25th patch was missing the new files, paravirt.{c,h}. (although I do remember having git-add'ed it, but who knows...)
Andrew, could you please push it
2013 Oct 15
0
[LLVMdev] [llvm-commits] r192750 - Enable MI Sched for x86.
...2 %X, i32 %Y) nounwind
>> define %0 @t3(i32 %lb, i8 zeroext %has_lb, i8 zeroext %lb_inclusive, i32 %ub, i8 zeroext %has_ub, i8 zeroext %ub_inclusive) nounwind {
>> entry:
>> ; DARWIN-LABEL: t3:
>> -; DARWIN: shll $16
>> ; DARWIN: shlq $32, %rcx
>> +; DARWIN-NEXT: orq %rcx, %rax
>> +; DARWIN-NEXT: shll $8
>> ; DARWIN-NOT: leaq
>> -; DARWIN: orq %rcx, %rax
>> %tmp21 = zext i32 %lb to i64
>> %tmp23 = zext i32 %ub to i64
>> %tmp24 = shl i64 %tmp23, 32
>>
>> Modified: llvm/trunk/test/CodeGen/X86/fast-isel-mem.ll...