search for: or1k

Hi - sorry to intrude, but can somebody point me to a suitable mailing list where a tyro can get some advice on modifying an existing llvm llvm assembler ... rather lightly? I want to add an extra instruction to the assembler/machine code supported by the OR1K llvm port. Well, there are a few more things I need to do, but that will be good enough to start with! I was able to what I wanted easily enough for gas, but I don't really see where to start with llvm. The files that do the business seem to be those with ".td" suffixes (which loo...

I'm trying to create a simplified 2 slot VLIW from an OR1K. The codebase I'm working with is here <https://github.com/openrisc/llvm-or1k>. I've created an initial MyTargetSchedule.td def MyTargetModel : SchedMachineModel { // HW can decode 2 instructions per cycle. let IssueWidth = 2; let LoadLatency = 4; let MispredictPenalty = 16;...

Thanks for the suggestion. I tried your fix. It worked for my particular case, but then I got a following error: clang-3.5: /home/rail/projects/escala_llvm/trunk/llvm-or1k/lib/CodeGen/RegisterPressure.cpp:39: void decreaseSetPressure(std::vector<unsigned int>&, llvm::PSetIterator): Assertion `CurrSetPressure[*PSetI] >= Weight && "register pressure underflow"' failed. Do you mind helping me out? A stack dump is provided below: clan...

...> > On 4/27/2016 3:44 PM, Rail Shafigulin wrote: > >> Thanks for the suggestion. >> >> I tried your fix. It worked for my particular case, but then I got a >> following error: >> >> clang-3.5: >> >> /home/rail/projects/escala_llvm/trunk/llvm-or1k/lib/CodeGen/RegisterPressure.cpp:39: >> void decreaseSetPressure(std::vector<unsigned int>&, >> llvm::PSetIterator): Assertion `CurrSetPressure[*PSetI] >= Weight && >> "register pressure underflow"' failed. >> >> Do you mind helping m...

....0-11 sun.cf: Sun Studio 12.0 & later compilers prefer -m32/-m64 README: reword status section Remove os2def.db from EXTRA_DIST xorg-cf-files 1.0.6 Andreas Boll (1): Imake.tmpl: Use gzip -n to not save the timestamps James Cloos (1): Minor adjustment to the or1k patch. Manuel A. Fernandez Montecelo (1): Add support for OpenRISC 1000 (or1k) CPU Riku Voipio (1): add DefaultGcc2AArch64Opt to xorg.cf Thomas Klausner (2): NetBSD: add AMD64Architecture, fix Arm32Architecture. Always include xorg.cf for GccAliasingArgs. git tag: xorg-c...

...; are enabled by default. > > This shouldn't break any out of tree backend, however, it may cause > misoptimisation if the backend dev do not activate these opcodes via > setOperationAction and rely on them for some of their optimizations. Thanks for heads up, this will impact the OR1K backend. Is there any guidance for migrating to U*O/*CARRY? -- whitequark

...afigulin wrote: > > Thanks for the suggestion. > > I tried your fix. It worked for my particular case, but then > I got a > following error: > > clang-3.5: > /home/rail/projects/escala_llvm/trunk/llvm-or1k/lib/CodeGen/RegisterPressure.cpp:39: > void decreaseSetPressure(std::vector<unsigned int>&, > llvm::PSetIterator): Assertion `CurrSetPressure[*PSetI] >= > Weight && > "register pressure underflow"' failed...

I was handed a makefile which is used to compile a library and was told to figure out why the compilation is failing. There is a lot of output and at this point I'm not sure what is important and what is not. I'm trying to solve this problem in small steps, so if asked I can certainly provide more information. The first error that I see during compilation is

These opcodes have been deprecated about a year ago, but still in use in various backend. In https://reviews.llvm.org/D47422 I would like to change the behavior of the backend to not enable the use of these opcodes by default. The opcode remains usable by any backend that wish to use them, but that should limit the situation where newer backend just use them as they are enabled by default. This

...ttps://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Zhu-Lingshan/IRQ-offloading-for-vDPA/20200716-192910 base: https://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost.git linux-next config: openrisc-randconfig-r016-20200717 (attached as .config) compiler: or1k-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILE...

Hi Si-Wei, Thank you for the patch! Yet something to improve: [auto build test ERROR on net/master] url: https://github.com/0day-ci/linux/commits/Si-Wei-Liu/failover-allow-name-change-on-IFF_UP-slave-interfaces/20190329-020744 config: openrisc-or1ksim_defconfig (attached as .config) compiler: or1k-linux-gcc (GCC) 6.0.0 20160327 (experimental) reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build t...