search for: opsize32

...6InstrArithmetic.td. I add ,(To make sure the Sched is right, I use the WriteIMul16Reg ) def max_qb : I<0xF0,MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), "max_qb\t {$dst, $src1,$src2}", [(set GR32:$dst,(X86max_qb GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul16Reg]>,OpSize32 ; when compile LLVM , the error appears. "[ 97%] Updating X86GenAsmWriter1.inc... Unhandled immediate encoding GR32 Unhandled immediate encoding " But when I write the same as the instruction IMUL32rr, there is no error in compiling.(I don't use the EFLAGS at all, so I think it...

...ing:implicit declaration of function 'int_x86_max_qb' is invalid in C99 [-Wimplicit-function-declaration]. So I add the definition in src/lib/Target/X86/X86InstrInfo.td def MAX_QB : I<0xff,RawFrm, (outs GR32:$Rd), (ins GR32:$src1,GR32:$src2),"max_qb \t $Rd $src1 $src2", []>, OpSize32; But it doesn't work.What should I do to make it correct? please tell me.Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180906/57706ad3/attachment.html>

...uot; is the most important and the defines the multiplication. def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),"imul{l}\t{$src2, $dst|$dst, $src2}", [(set GR32:$dst, EFLAGS, (X86smul_flag GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul32Reg]>, TB, OpSize32; And in X86ScheduleXXX.td ,there is definition of Ports and so on. My questions are here,as following: 1.whether the schedule of an instruction defines the machine how to do. 2.Why is there no "add" or "sub" instructions("ALU insturctions") in X86InstrArithmetic.td?...

...get/X86/X86InstrArithmetic.td: def max_qb : I<0xff,MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), "max_qb\t {$dst, $src1,$src2|$src1,$src2, $dst}", [(set GR32:$dst,EFLAGS,(X86max_qb_flag GR32:$src1, GR32:$src2))]>, Sched<[WriteIMul]>, TB, OpSize32 ; I think it can be work ,at least work as one multiplication(because I use the Sched<[WriteIMul]>). But there is an error :"error: use of unknown builtin '__builtin_x86_max_qb'". And I don't konw what I should do. Thanks a lot. -------------- next part -------------- A...

...uot; is the most important and the defines the multiplication. def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),"imul{l}\t{$src2, $dst|$dst, $src2}", [(set GR32:$dst, EFLAGS, (X86smul_flag GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul32Reg]>, TB, OpSize32; And in X86ScheduleXXX.td ,there is definition of Ports and so on. My questions are here,as following: 1.whether the schedule of an instruction defines the machine how to do. 2.Why is there no "add" or "sub" instructions("ALU insturctions") in X86InstrArithmetic.td?...

...R, 5, "selectAddr", [], [SDNPWantParent]>; The derefencing mov instruction looks like this: def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), "mov{l}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32; So it expects a source address of type 'addr' which is 8 bytes. This leads to the following code being emitted when I apply my solution to problem 1: mov (%rcx),%eax In other words, the upper bits are not ignored. I am currently not sure what is the best place to solve this pro...

...gister encoded in bits 7:4 Imm16 Imm16PCRel Imm32 - 32-bit immediate Imm32PCRel Imm32S - 32-bit immediate that is sign extended to 64-bits. Imm64 Opsize ------ OpSizeFixed(default) - Operand size isn't mode dependent OpSize16 - 0x66 prefix required in 32-bit mode OpSize32 - 0x66 prefix required in 16-bit mode OpSizeIgnored - 0x66 prefix should be ignored if present. Adsize ------ AdSizeX(default) - Address size prefix determined from memory operand registers encoded in modrm byte AdSize16 - Need a 0x67 prefix in 32-bit mode AdSize...

...ot;, [], > [SDNPWantParent]>; > The derefencing mov instruction looks like this: > def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), > "mov{l}\t{$src, $dst|$dst, $src}", > [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32; > So it expects a source address of type 'addr' which is 8 bytes. This > leads to the following code being emitted when I apply my solution to > problem 1: > mov (%rcx),%eax > In other words, the upper bits are not ignored. > > > I am currently not sure wh...

I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML

...ry operands? As an example, consider the following description of MOV32mr (from X86InstrInfo.td) def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), "mov{l}\t{$src, $dst|$dst, $src}", [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32; or that of MOVSX64rm (from X86InstrExtension.td) def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), "movs{lq|xd}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (sextloadi64i32 addr:$src))], IIC_MOVSX>,...

Hi, I'm trying to revive jacobly0's Z80 back-end (from https://github.com/jacobly0/llvm-z80) and build it with a current version of LLVM. Apart from some interface changes, I'm stuck at building the tables. Specifically, the generation of the DAG instruction selector causes an assertion in the table generator: Assertion failed: Ops.size() >= NumSrcResults &&