Displaying 2 results from an estimated 2 matches for "operarand".
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operaand
2007 Sep 27
3
[LLVMdev] Vector swizzling and write masks code generation
...rdware (basically every single programmable gpu) has
instruction level support for vector swizzling and write masks.
For example the following represents a valid gpu shader instruction:
ADD dst.xyz src1.yxzw src2.zwxy
which performs an addition that stores the result to the dst operated (each
operarand is a vector type of four data elements) The instruction uses source
swizzle modifiers and destination mask modifier.
So if a language is capable of expressing such constructs (as GLSL, HLSL and
few others are) I'd like to make sure that the code generator is actually
capable of generating i...
2007 Sep 27
0
[LLVMdev] Vector swizzling and write masks code generation
...gle programmable gpu) has
> instruction level support for vector swizzling and write masks.
ok
> For example the following represents a valid gpu shader instruction:
> ADD dst.xyz src1.yxzw src2.zwxy
> which performs an addition that stores the result to the dst operated (each
> operarand is a vector type of four data elements) The instruction uses source
> swizzle modifiers and destination mask modifier.
Right.
> So if a language is capable of expressing such constructs (as GLSL, HLSL and
> few others are) I'd like to make sure that the code generator is actually
>...