Displaying 4 results from an estimated 4 matches for "operaand".
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operand
2012 Jul 05
2
[LLVMdev] bug in tablegen?
...[(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))],
!cast<FRRR16_ins>(I).Itinerary > {
let isCommutable = isComm;
let isReMaterializable = 1;
}
def foo: ArithLogicRTest16<"AdduRxRyRz16", add, 1>;
I think that the problem has to do with the operaand lists not working
if there is substitution
required.
Tablegen is only complaining about $rx, $ry and $rz .
On 07/03/2012 05:35 PM, Sean Silva wrote:
> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
> InstrItinClass itin> : // ...
>
> This class ha...
2012 Jul 05
0
[LLVMdev] bug in tablegen?
...gs:$ry, CPU16Regs:$rz))],
> !cast<FRRR16_ins>(I).Itinerary> {
> let isCommutable = isComm;
> let isReMaterializable = 1;
> }
>
> def foo: ArithLogicRTest16<"AdduRxRyRz16", add, 1>;
>
> I think that the problem has to do with the operaand lists not working
> if there is substitution
> required.
>
> Tablegen is only complaining about $rx, $ry and $rz .
>
> On 07/03/2012 05:35 PM, Sean Silva wrote:
>> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
>> InstrItinClass itin&...
2012 Jul 04
0
[LLVMdev] bug in tablegen?
class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
InstrItinClass itin> : // ...
This class has template args. You don't specify them in the first
template arg of
class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ...
--Sean Silva
On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote:
> Not sure what you mean.
2012 Jul 03
3
[LLVMdev] bug in tablegen?
Not sure what you mean.
I.OutOperandList == (outs CPU16Regs:$rx)
I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz)
On 07/02/2012 09:26 PM, Sean Silva wrote:
> I think you're missing the template args for `FRRR16_ins` in the first
> argument. The switch in TGParser::ParseType() doesn't cover the case
> of types with template args though... which makes me wonder what is