search for: opc2

Displaying 12 results from an estimated 12 matches for "opc2".

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2014 Jul 31
5
[LLVMdev] Tablegen binary literals
Hi Adam > On Jul 30, 2014, at 10:28 PM, Adam Nemet <anemet at apple.com> wrote: > > Hi Pete, > > Just to clarify, are you proposing two things here? First, 0b… literals to have type bits<n> and second to allow bits<n> initializer to contain other bits<m> elements which would initialize the next m elements. > Yeah, exactly those 2 things. I have them
2008 Oct 07
2
[LLVMdev] Making Sense of ISel DAG Output
...some somewhat-seemingly-reasonably-correct matching and generation code. What's happening is that that generation code constructs two MOVSD2PD instructions. These are all brand-new SDNodes. The very last step of the generation code calls SDNode *RetVal = CurDAG->SelectNodeTo(N.Val, Opc2, VT2, Tmp1, Tmp3, Tmp5); where N is the vector_shuffle node. and the Tmp variables are the two MOVSD2PD instructions and the shuffle mask. SelectNodeTo does an in-place replacement of the machine-independent SDNode (vector_shuffle)with a machine-dependent one (the SHUFPD). When we pop back o...
2014 Jul 31
2
[LLVMdev] Tablegen binary literals
...ed binary literals if we also allow > them to initialize multiple bits in another bits<n> type. > > > Looks like bits<n> is already valid in a bits initializer context; it > yields the bottom bit. > > def a { > bits<2> opc = { 0, 1 }; > bits<2> opc2 = { 1, 0 }; > bits<2> oo = { opc, opc2 }; > } > > is valid and produces: > > .. > bits<2> oo = { 1, 0 }; > .. > > Are you aware of this? This may lead to some ambiguity with your proposed > extension. (I have no idea whether this behavior is relied...
2008 Oct 07
0
[LLVMdev] Making Sense of ISel DAG Output
...ably-correct matching and generation code. > > What's happening is that that generation code constructs two MOVSD2PD > instructions. These are all brand-new SDNodes. The very last step > of the > generation code calls > > SDNode *RetVal = CurDAG->SelectNodeTo(N.Val, Opc2, VT2, Tmp1, Tmp3, > Tmp5); > > where N is the vector_shuffle node. and the Tmp variables are the two > MOVSD2PD instructions and the shuffle mask. SelectNodeTo does an in- > place > replacement of the machine-independent SDNode (vector_shuffle)with a > machine-dependent on...
2008 Oct 03
0
[LLVMdev] Making Sense of ISel DAG Output
On Fri, October 3, 2008 9:10 am, David Greene wrote: > On Thursday 02 October 2008 19:32, Dan Gohman wrote: > >> Looking at your dump() output above, it looks like the pre-selection >> loads have multiple uses, so even though you've managed to match a >> larger pattern that incorporates them, they still need to exist to >> satisfy some other users. > > Yes,
2008 Oct 03
3
[LLVMdev] Making Sense of ISel DAG Output
On Thursday 02 October 2008 19:32, Dan Gohman wrote: > Looking at your dump() output above, it looks like the pre-selection > loads have multiple uses, so even though you've managed to match a > larger pattern that incorporates them, they still need to exist to > satisfy some other users. Yes, I looked at that too. It looks like these other uses end up being chains to
2013 May 30
9
[PATCH v2 0/2] Implement VFP context switch for arm32
Hello, This is the second version of this patch series. I only implement the VPF context switch support for arm32 and add dummy function to avoid compilation on arm64. I have switched the order of the patch because the old second one can be applied alone and the patch are cleaner :). For all the changes see each patch. Cheers, Julien Grall (2): xen/arm: don''t enable VFP on XEN
2017 Mar 26
5
[PATCH v5 0/5] nvc0/ir: add support for MAD/FMA PostRALoadPropagation
was "nv50/ir: PostRaConstantFolding improvements" before. nothing really changed from the last version, just minor things. Karol Herbst (5): nv50/ir: restructure and rename postraconstantfolding pass nv50/ir: implement mad post ra folding for nvc0+ gk110/ir: add LIMM form of mad gm107/ir: add LIMM form of mad nv50/ir: also do PostRaLoadPropagation for FMA
2013 Feb 22
48
[PATCH v3 00/46] initial arm v8 (64-bit) support
This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.
2013 Jan 23
132
[PATCH 00/45] initial arm v8 (64-bit) support
First off, Apologies for the massive patch series... This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8 (AArch64) model. The kernel is the same one as I am currently using with the 32 bit hypervisor I haven''t yet tried starting a guest or anything super advanced like that ;-). Also there is not real support for 64-bit domains at all, although in one or two places I
2012 Jan 09
39
[PATCH v4 00/25] xen: ARMv7 with virtualization extensions
Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See
2011 Dec 06
57
[PATCH RFC 00/25] xen: ARMv7 with virtualization extensions
Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See