search for: op_addi

Hi Adam, John is right, the TCE stuff would be useful for you. Our compiler targets a processor template that the designer can populate pretty freely. The compiler then reads the architecture description and creates an LLVM backend on the fly. Please don't hesitate to get in touch with us if you have questions. -- Pertti

Hello gyus, I am working on a project, where we are trying to create a development environment for new ASIP processor design. Part of this project is a compiler generator, where we would like to generate C compiler from some instruction description. To keep it short, let's say, that in each instruction's semantics is described by some C code. What I would like to do is to compile this

...ry bit-width integers: I can extract from our architecture description language ISAC code, that for each instruction tells what it does: Syntax: MIPS instrucion ADDDI "ADDI" reg(0) "," reg(1) "," imm(2) Semantics: unsigned int gpregs[32]; void instr_direct_rri$op_addi$imm16$() { int op_arithm_imm = 0x08; { int rt = 1; { int rs = 28; { short imm16 = imm_i16(2); //--- intrinsics, represents instruction's immediate operand { { int simm = ((int)(imm16) << (32 - (16))) >> (32 - (16)); switch (op_arithm_imm) { //.... case 0x08: case 0x09: {if (rt !...