Displaying 7 results from an estimated 7 matches for "op3val".
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op2val
2007 Oct 19
0
[LLVMdev] Adding address registers to back-end
...)) during lowering. I assume the code-generator cant place values
> in the address registers? All address-registers are elements in the
> register sets IntRegs and AddrRegs.
/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
def rr : F3_1<2, Op3Val,
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
!strconcat(OpcStr, " $b, $c, $dst"),
[(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:
$c))]>;
def ri : F3_2<2, Op3Val,...
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
...amentals.html#multiclass
Basically this lets you use one definition to implement multiple different
instructions. For example, most instructions in the sparc target come in
"reg,reg" and "reg,imm" forms. As such, it defines:
multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
def rr : F3_1<2, Op3Val,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
!strconcat(OpcStr, " $b, $c, $dst"),
[(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
def ri : F3_2<2, Op3Val,...
2007 Oct 19
2
[LLVMdev] Adding address registers to back-end
Hi!
I'm writing a new back-end for a new architecture. First, I'll do
some "tests" with an existing back-end (I chose the Sparc back-end).
My architecture has special address-registers and I want to add such
new address-registers to my Sparc back-end.
1) I defined a new register call AddrRegs
2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. ))
3) I
2006 Oct 01
2
[LLVMdev] Instruction descriptions question
Hi,
I'm trying to implement a new backend for an embedded CISC processor.
Therefore I thought that it makes sense to take X86 target as a basis,
to save some time.
But when I look into the X86InstrInfo.td, I have a very strong feeling
that it is one of the most complex instruction set descriptions
compared to other targets. I can imagine that this is due to the
complexity of X86's
2011 Nov 08
0
[LLVMdev] Newbie Question: How are the values set in a Sparc store instruction (e.g. STri)?
...STri : F3_2<3, 0b000100,
(outs), (ins MEMri:$addr, IntRegs:$src),
"st $src, [$addr]",
[(store IntRegs:$src, ADDRri:$addr)]>;
F3_2 and it's superclasses are defined as follows:
class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr,
pattern> {
bits<13> simm13;
let op = opVal;
let op3 = op3val;
let Inst{13} = 1; // i field = 1
let Inst{12-0} = simm13;
}
class F3<dag outs, dag ins, st...
2007 Oct 21
1
[LLVMdev] Adding address registers to back-end
...assume the code-generator cant place values
>> in the address registers? All address-registers are elements in the
>> register sets IntRegs and AddrRegs.
>
> /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
> multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
> ....
> }
>
> defm ADD : F3_12<"add", 0b000000, add>;
>
> Instruction ADD output register class is IntRegs. It does not match
> AddrRegs. That's why you are getting the assertion.
The address register set AddrRegs is a subset of In...
2006 Oct 02
2
[LLVMdev] Instruction descriptions question
...> Basically this lets you use one definition to implement multiple
different
> instructions. For example, most instructions in the sparc target
come in
> "reg,reg" and "reg,imm" forms. As such, it defines:
>
> multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
> def rr : F3_1<2, Op3Val,
> (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
> !strconcat(OpcStr, " $b, $c, $dst"),
> [(set IntRegs:$dst, (OpNode IntRegs:$b,
IntRegs:$c))]>;
> def ri : F3_2...