Displaying 5 results from an estimated 5 matches for "oneinoneout".
2008 Oct 06
1
[LLVMdev] sign extensions on loads?
...e:$ptr), (ld node:$ptr), [{
return isGenericLoad(dyn_cast<LoadSDNode>(N));
}]>;
def ADDRf : ComplexPattern<i32, 2, "SelectADDRf", [frameindex], []>;
// Load Memory Operations
multiclass LOADm<string asm, PatFrag OpNode, ComplexPattern addr> {
def _i32 : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins MEM:$ptr),
asm, [(set (i32 GPR:$dst), (OpNode addr:$ptr))]>;
def _f32 : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins MEM:$ptr),
asm, [(set (f32 GPR:$dst), (OpNode addr:$ptr))]>;
def _i64 : OneInOneOut<IL_OP_MOV, (outs GPR:$...
2008 Sep 23
1
[LLVMdev] Tablegen strings
I have a tablegen string that I want to add a modifier to the registers
that are being matched.
For example a simple match on fneg:
def FNEG : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins
GPR:$src0),
"mov $dst, $src0", [(set GPR:$dst, (fneg GPR:$src0))]>;
I want to place a modifier directly after $src0 in the string so that no
space is between the string
and the matched register. I.e. I want to generate "mov $dst, $s...
2008 Sep 23
2
[LLVMdev] Store patterns accepting i32 only?
...de<"AMDILISD::GLOBAL_STORE", SDTStore,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def global_store : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
return isGlobalStore(dyn_cast<StoreSDNode>(N));
}]>;
def GLOBALSTORE : OneInOneOut<IL_OP_MOV, (outs), (ins GPR:$val,
MEM:$ptr),
"mov g[$ptr], $val",
[(global_store GPR:$val, ADDR:$ptr)]>;
I want this same pattern to be able to accept all the types for val that
GPR is mapped to(i32, i64, f32, f64).
Is there any...
2008 Sep 23
0
[LLVMdev] Store patterns accepting i32 only?
...OBAL_STORE", SDTStore,
> [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
>
> def global_store : PatFrag<(ops node:$val, node:$ptr),
> (st node:$val, node:$ptr), [{
> return isGlobalStore(dyn_cast<StoreSDNode>(N));
> }]>;
> def GLOBALSTORE : OneInOneOut<IL_OP_MOV, (outs), (ins GPR:$val, MEM:
> $ptr),
> "mov g[$ptr], $val",
> [(global_store GPR:$val, ADDR:$ptr)]>;
>
> I want this same pattern to be able to accept all the types for val
> that GPR is mapped to(i32, i...
2008 Sep 10
2
[LLVMdev] Custom Lowering and fneg
...ting to pattern match on an
i32 when there are no i32's in my test program.
I've tried a custom lowering function that lowers it to dst = sub 0,
src0 and forcing it to f32, but it complains that result and the op
value types are incorrect.
My table descriptor rule is:
def FNEG : OneInOneOut<OP_F_NEG, (outs GPR:$dst), (ins GPR:$src0),
!strconcat(OP_F_NEG.Text, " $dst, $src0"),
[(set GPR:$dst, (fneg GPR:$src0))]>;
With GPR defined as either an i32 or an f32.
On another not, is there any known examples of...