Displaying 5 results from an estimated 5 matches for "offsetreg".
2016 Sep 26
2
Incompatible type assertion from llvm-tblgen
...>
: Operand<i64>,
ComplexPattern< i64, numArgs, funcName, [], [SDNPWantParent] > {
let MIOperandInfo = opInfo;
}
let PrintMethod = "printMemOperand" in {
def ADDR_RR : Addr< 2, "SelectAddrRegReg",
(ops GPRC:$base, GPRC:$offsetreg) >;
def ADDR_RI : Addr< 2, "SelectAddrRegImm",
(ops GPRC:$base, i64imm:$offsetimm) >;
def ADDR_SHLI : Addr< 2, "SelectAddrShlImm",
(ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >;
}
If I change the LoadOpIdx de...
2016 Sep 28
2
Incompatible type assertion from llvm-tblgen
...<
kparzysz at codeaurora.org> wrote:
> On 9/26/2016 3:58 PM, Phil Tomson wrote:
>
>> But don't the defs for ADDR_RR and ADDR_RI also contain dags?
>>
>> def ADDR_RR : Addr< 2, "SelectAddrRegReg",
>> (ops GPRC:$base, GPRC:$offsetreg) >;
>> def ADDR_RI : Addr< 2, "SelectAddrRegImm",
>> (ops GPRC:$base, i64imm:$offsetimm) >;
>>
>> Do I need to create some other intermediate node type for a shifted
>> address?
>>
>
> Technically yes, but the list...
2016 Sep 26
2
Incompatible type assertion from llvm-tblgen
But don't the defs for ADDR_RR and ADDR_RI also contain dags?
def ADDR_RR : Addr< 2, "SelectAddrRegReg",
(ops GPRC:$base, GPRC:$offsetreg) >;
def ADDR_RI : Addr< 2, "SelectAddrRegImm",
(ops GPRC:$base, i64imm:$offsetimm) >;
Do I need to create some other intermediate node type for a shifted address?
Phil
On Mon, Sep 26, 2016 at 1:42 PM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at li...
2016 Oct 04
2
Incompatible type assertion from llvm-tblgen
...+ (r3 << sizeof(operand))]
>>
>> That somehow the pattern matching dag fragment would need to be
>> something like I had in ADDR_SHLI definition:
>> def ADDR_SHLI : Addr< 2, "SelectAddrShlImm",
>> (ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >;
>>
>>
>> Now If I have to create a subclass of Operand and define it's
>> EncoderMethod in C++, does that mean the pattern matching (matching the
>> shift left and add) now happens on the C++ side as well?
>>
>
> Actually the EncoderMet...
2020 Mar 12
3
Getting up to speed with llvm backends. Machine Instruction operands.
...I would like to target the Hitachi/Motorola
6309/6809 which too
provides dedicated indexing (addressing) registers. In fact in all binary
operations the second
operand is either immediate or some kind of a memory reference via a
index/address register.
The syntax being:
{[}{OffsetReg | Disp{5,8,16}},{- | --}IndexReg{+ | ++ | ]}
OffsetReg can be 8bit or 16bit accumulator (so only certain regs allowed)
Displacment can be 5, 8 or 16 bit signed
IndexReg can only be special index registers or PC or stack
+ ++ is post increment by 1, 2 repsectively
- -- is pre decrement by 1,...