search for: nxv4i32

Displaying 11 results from an estimated 11 matches for "nxv4i32".

2017 Mar 07
2
[RFC][SVE] Extend vector types to support SVE registers.
...; it seems logical to use the same scheme for SVE but also incorporate the implicit (VL x) to distinguish from existing vector types. Hence we are proposing each vector MVT have a scalable vector MVT equivalent. MVT::v2i32 -> MVT::nxv2i32 MVT::v2i64 -> MVT::nxv2i64 MVT::v4i32 -> MVT::nxv4i32 MVT::v4i64 -> MVT::nxv4i64 ....likewise for all <#Elements> and <ElementType> combinations The resulting SVE instruction selection is... (1) Pat<(nxv2i64 (add (nxv2i64 $zn), (nxv2i64 $zm))), ADD_D_ZZZ // New SVE pattern (2) Pat<(nxv4i32 (add (nxv4i32 $zn), (nxv4i32 $zm))),...
2018 Jun 05
2
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...r evolution sequence like {start, op, step}. In C++'s iota (AFAICS), the step is always 1. Anyway, I don't mind any name, really. Whatever is more mnemonic. > ;; Create sequence for scalable vector > %stepvector = call <scalable 4 x i32> @llvm.experimental.vector.stepvector.nxv4i32() > %mulbystride = mul <scalable 4 x i32> %stepvector, %str_off > %addoffset = add <scalable 4 x i32> %mulbystride, %str_off Once stepvetor (or iota) becomes a proper IR instruction, I'd like to see this restricted to inlined syntax. The sequence { step*vec + offset } only...
2016 Nov 04
2
[RFC] Supporting ARM's SVE in LLVM
...ve the same number of elements. `<n x 4 x i32>` and `<n x 8 x i16>` have the same number of bytes. ## SelectionDAG New scalable vector MVTs are added, one for each existing vector type. Scalable vector MVTs are modelled in the same way as the IR. Hence, `<n x 4 x i32>` becomes `nxv4i32`. ## MVT Interface: ```cpp static MVT getVectorVT(MVT VT, ElementCount EC); bool isScalableVector() const; static mvt_range integer_scalable_valuetypes(); static mvt_range fp_scalable_valuetypes(); ``` To minimise the effort required for common code to preserve the scalable flag we exten...
2019 May 24
2
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...2> under, i32 2, i32 0 > %str_off = shufflevector <scalable 4 x i32> %insert2, <scalable 4 x i32> undef, <scalable 4 x i32> zeroinitializer > ;; Create sequence for scalable vector > %stepvector = call <scalable 4 x i32> @llvm.experimental.vector.stepvector.nxv4i32() > %mulbystride = mul <scalable 4 x i32> %stepvector, %str_off > %addoffset = add <scalable 4 x i32> %mulbystride, %str_off > ;; Add the runtime-generated sequence > %add = add <scalable 4 x i32> %splat, %addoffset > `` > Future Work > ----------- &gt...
2018 Jun 05
14
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...scalable 4 x i32> under, i32 2, i32 0 %str_off = shufflevector <scalable 4 x i32> %insert2, <scalable 4 x i32> undef, <scalable 4 x i32> zeroinitializer ;; Create sequence for scalable vector %stepvector = call <scalable 4 x i32> @llvm.experimental.vector.stepvector.nxv4i32() %mulbystride = mul <scalable 4 x i32> %stepvector, %str_off %addoffset = add <scalable 4 x i32> %mulbystride, %str_off ;; Add the runtime-generated sequence %add = add <scalable 4 x i32> %splat, %addoffset `` Future Work ----------- Intrinsics cannot currently be used f...
2018 Jul 30
5
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...i32> under, i32 2, i32 0 > %str_off = shufflevector <scalable 4 x i32> %insert2, <scalable 4 x i32> undef, <scalable 4 x i32> zeroinitializer > ;; Create sequence for scalable vector > %stepvector = call <scalable 4 x i32> @llvm.experimental.vector.stepvector.nxv4i32() > %mulbystride = mul <scalable 4 x i32> %stepvector, %str_off > %addoffset = add <scalable 4 x i32> %mulbystride, %str_off > ;; Add the runtime-generated sequence > %add = add <scalable 4 x i32> %splat, %addoffset > `` > Future Work > ----------- > &...
2019 May 24
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...scalable 4 x i32> under, i32 2, i32 0 %str_off = shufflevector <scalable 4 x i32> %insert2, <scalable 4 x i32> undef, <scalable 4 x i32> zeroinitializer ;; Create sequence for scalable vector %stepvector = call <scalable 4 x i32> @llvm.experimental.vector.stepvector.nxv4i32() %mulbystride = mul <scalable 4 x i32> %stepvector, %str_off %addoffset = add <scalable 4 x i32> %mulbystride, %str_off ;; Add the runtime-generated sequence %add = add <scalable 4 x i32> %splat, %addoffset `` Future Work ----------- Intrinsics cannot currently be used f...
2019 May 27
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...scalable 4 x i32> under, i32 2, i32 0 %str_off = shufflevector <scalable 4 x i32> %insert2, <scalable 4 x i32> undef, <scalable 4 x i32> zeroinitializer ;; Create sequence for scalable vector %stepvector = call <scalable 4 x i32> @llvm.experimental.vector.stepvector.nxv4i32() %mulbystride = mul <scalable 4 x i32> %stepvector, %str_off %addoffset = add <scalable 4 x i32> %mulbystride, %str_off ;; Add the runtime-generated sequence %add = add <scalable 4 x i32> %splat, %addoffset `` Future Work ----------- Intrinsics cannot currently be used f...
2019 Jun 03
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...2> under, i32 2, i32 0 > %str_off = shufflevector <scalable 4 x i32> %insert2, <scalable 4 x i32> undef, <scalable 4 x i32> zeroinitializer > ;; Create sequence for scalable vector > %stepvector = call <scalable 4 x i32> @llvm.experimental.vector.stepvector.nxv4i32() > %mulbystride = mul <scalable 4 x i32> %stepvector, %str_off > %addoffset = add <scalable 4 x i32> %mulbystride, %str_off > ;; Add the runtime-generated sequence > %add = add <scalable 4 x i32> %splat, %addoffset > `` > Future Work > ----------- &gt...
2018 Jul 30
7
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...str_off = shufflevector <scalable 4 x i32> %insert2, <scalable > 4 x i32> undef, <scalable 4 x i32> zeroinitializer > >  ;; Create sequence for scalable vector > >  %stepvector = call <scalable 4 x i32> > @llvm.experimental.vector.stepvector.nxv4i32() > >  %mulbystride = mul <scalable 4 x i32> %stepvector, %str_off > >  %addoffset = add <scalable 4 x i32> %mulbystride, %str_off > >  ;; Add the runtime-generated sequence > >  %add = add <scalable 4 x i32> %splat, %addoffset > >...
2018 Jul 02
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...t; under, i32 2, i32 0 > %str_off = shufflevector <scalable 4 x i32> %insert2, <scalable 4 x i32> undef, <scalable 4 x i32> zeroinitializer > ;; Create sequence for scalable vector > %stepvector = call <scalable 4 x i32> @llvm.experimental.vector.stepvector.nxv4i32() > %mulbystride = mul <scalable 4 x i32> %stepvector, %str_off > %addoffset = add <scalable 4 x i32> %mulbystride, %str_off > ;; Add the runtime-generated sequence > %add = add <scalable 4 x i32> %splat, %addoffset > `` > Future Work > -----------...