search for: nvptxinst

Hi Guys, In LLVM codegen, a typical binary operation instruction is defined something like below: " def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b), "xor.pred \t$dst, $a, $b;", [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>; “ which takes two inputs and write the result to the $dst register. Then how to define a binary instruction which returns tw...

...work, or is that a known limitation in the current implementation? If I have TableGen code like the following... 1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>; 1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>; 1244 1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1), 1246 (ins Int32Regs:$a), 1247 "test $dst0, $dst1, $a;", 1248 [(set Int32Regs:$dst0, Int32Regs:$dst1, (TestNode Int32Regs:$a))]>; ... TableGen crashes with the f...

...s > with multiple outputs. > > > If I have TableGen code like the following... > > 1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>; > 1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>; > 1244 > 1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1), > 1246 (ins Int32Regs:$a), > 1247 "test $dst0, $dst1, $a;", > 1248 [(set Int32Regs:$dst0, Int32Regs:$dst1, > (TestNode Int32Regs:$a))]>; > > .....

...atterns with multiple outputs. > > If I have TableGen code like the following... > > 1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>; > 1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>; > 1244 > 1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1), > 1246 (ins Int32Regs:$a), > 1247 "test $dst0, $dst1, $a;", > 1248 [(set Int32Regs:$dst0, Int32Regs:$dst1, (TestNode Int32Regs:$a))]>; > > ... Ta...

...t; >> >> If I have TableGen code like the following... >> >> 1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>; >> 1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>; >> 1244 >> 1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1), >> 1246 (ins Int32Regs:$a), >> 1247 "test $dst0, $dst1, $a;", >> 1248 [(set Int32Regs:$dst0, Int32Regs:$dst1, (TestNode Int32Regs:$a))]>; >&...

I'm building this with llvm-c, and accessing these intrinsics via calling the intrinsic as if it were a function. class F_SREG<string OpStr, NVPTXRegClass regclassOut, Intrinsic IntOp> : NVPTXInst<(outs regclassOut:$dst), (ins), OpStr, [(set regclassOut:$dst, (IntOp))]>; def INT_PTX_SREG_TID_X : F_SREG<"mov.u32 \t$dst, %tid.x;", Int32Regs, int_nvvm_read_ptx_sreg_tid_x>; This method of accessing intrinsics works just fine for other intrinsics...

Dear all, Let's say there is some complex tblgen intrinsic definition, for example: class MEMBAR<string StrOp, Intrinsic IntOP> : NVPTXInst<(outs), (ins), StrOp, [(IntOP)]>; def INT_MEMBAR_CTA : MEMBAR<"membar.cta;", int_nvvm_membar_cta>; def INT_MEMBAR_GL : MEMBAR<"membar.gl;", int_nvvm_membar_gl>; def INT_MEMBAR_SYS : MEMBAR<"membar.sys;", int_nvvm_membar_sys>; Que...

...instance, nvptx regression tests. ----- Original message ----- > I'm building this with llvm-c, and accessing these intrinsics via calling > the intrinsic as if it were a function. > > class F_SREG<string OpStr, NVPTXRegClass regclassOut, Intrinsic IntOp> : >            NVPTXInst<(outs regclassOut:$dst), (ins), >                              OpStr, >                  [(set regclassOut:$dst, (IntOp))]>; > > def INT_PTX_SREG_TID_X : F_SREG<"mov.u32 \t$dst, %tid.x;", Int32Regs, >    int_nvvm_read_ptx_sreg_tid_x>; > > This method...

...lt;cameron.mcinally at nyu.edu> wrote: > On Mon, Jun 16, 2014 at 4:51 PM, kewuzhang <kewu.zhang at amd.com> wrote: >> Hi Guys, >> >> In LLVM codegen, >> a typical binary operation instruction is defined something like below: >> >> " def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b), >> "xor.pred \t$dst, $a, $b;", >> [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>; >> “ >> >> which takes two inputs and write the result to the $dst register. >> >...

...3 at 11:51 AM, Timothy Baldridge <tbaldridge at gmail.com> wrote: > I'm building this with llvm-c, and accessing these intrinsics via calling > the intrinsic as if it were a function. > > class F_SREG<string OpStr, NVPTXRegClass regclassOut, Intrinsic IntOp> : > NVPTXInst<(outs regclassOut:$dst), (ins), > OpStr, > [(set regclassOut:$dst, (IntOp))]>; > > def INT_PTX_SREG_TID_X : F_SREG<"mov.u32 \t$dst, %tid.x;", Int32Regs, > int_nvvm_read_ptx_sreg_tid_x>; > > This method of accessing intrinsics work...

...ge <tbaldridge at gmail.com> > wrote: > > I'm building this with llvm-c, and accessing these intrinsics via calling > > the intrinsic as if it were a function. > > > > class F_SREG<string OpStr, NVPTXRegClass regclassOut, Intrinsic IntOp> : > > NVPTXInst<(outs regclassOut:$dst), (ins), > > OpStr, > > [(set regclassOut:$dst, (IntOp))]>; > > > > def INT_PTX_SREG_TID_X : F_SREG<"mov.u32 \t$dst, %tid.x;", Int32Regs, > > int_nvvm_read_ptx_sreg_tid_x>; > > > > This...

Timothy, Those calls to compute grid intrinsics are definitely wrong. In ptx code they should end up into reading special registers, rather than function calls. Try to take some working example and figure out the LLVM IR differences between it and the result of your compiler. - D. ----- Original message ----- > I've written a compiler that outputs PTX code, the result seems fairly >

I've written a compiler that outputs PTX code, the result seems fairly reasonable, but I'm not sure the intrinsics are getting compiled correctly. In addition, when I try load the module using CUDA, I get an error: CUDA_ERROR_NO_BINARY_FOR_GPU. I'm running this on a 2012 MBP with a 640M GPU. PTX Code (for a mandelbrot calculation): // // Generated by LLVM NVPTX Back-End //