Displaying 17 results from an estimated 17 matches for "nvkm_sclass".
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nvkm_oclass
2019 Oct 09
0
[PATCH] drm/nouveau/core/client: make nvkm_uclient_sclass static
...vers/gpu/drm/nouveau/nvkm/core/client.c
index ac671202919e..0c8c55c73b12 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/client.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/client.c
@@ -60,7 +60,7 @@ nvkm_uclient_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
return 0;
}
-const struct nvkm_sclass
+static const struct nvkm_sclass
nvkm_uclient_sclass = {
.oclass = NVIF_CLASS_CLIENT,
.minver = 0,
--
2.23.0
2016 Nov 02
0
[PATCH v3 01/15] core: constify nv*_printk macros
...->oclass, ##a); \
diff --git a/drm/nouveau/include/nvkm/core/device.h b/drm/nouveau/include/nvkm/core/device.h
index 6bc712f32c8b..d426b86e2712 100644
--- a/drm/nouveau/include/nvkm/core/device.h
+++ b/drm/nouveau/include/nvkm/core/device.h
@@ -262,7 +262,7 @@ extern const struct nvkm_sclass nvkm_udevice_sclass;
/* device logging */
#define nvdev_printk_(d,l,p,f,a...) do { \
- struct nvkm_device *_device = (d); \
+ const struct nvkm_device *_device = (d); \
if (_device->debu...
2016 Dec 13
0
[PATCH v2 1/15] core: constify nv*_printk macros
...->oclass, ##a); \
diff --git a/drm/nouveau/include/nvkm/core/device.h b/drm/nouveau/include/nvkm/core/device.h
index 6bc712f32c8b..d426b86e2712 100644
--- a/drm/nouveau/include/nvkm/core/device.h
+++ b/drm/nouveau/include/nvkm/core/device.h
@@ -262,7 +262,7 @@ extern const struct nvkm_sclass nvkm_udevice_sclass;
/* device logging */
#define nvdev_printk_(d,l,p,f,a...) do { \
- struct nvkm_device *_device = (d); \
+ const struct nvkm_device *_device = (d); \
if (_device->debu...
2018 Jan 26
0
[RFC v3 2/4] drm/nouveau: Add support for BLCG on Kepler1
...--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
@@ -137,6 +137,7 @@ struct gf100_gr_func {
int (*rops)(struct gf100_gr *);
int ppc_nr;
const struct gf100_grctx_func *grctx;
+ const struct nvkm_therm_clkgate_pack *clkgate_pack;
struct nvkm_sclass sclass[];
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
index 5e82f94c2245..17cea9c70f7f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
@@ -22,6 +22,7 @@
* Author...
2016 Dec 06
0
[PATCH 3/8] core: add falcon library functions
...ruct nvkm_falcon *, struct nvkm_gpuobj *);
+ int (*wait_for_halt)(struct nvkm_falcon *, u32);
+ void (*set_start_addr)(struct nvkm_falcon *, u32 start_addr);
+ void (*start)(struct nvkm_falcon *);
+ int (*enable)(struct nvkm_falcon *falcon);
+ void (*disable)(struct nvkm_falcon *falcon);
+
struct nvkm_sclass sclass[];
};
+
+struct nvkm_falcon *nvkm_falcon_get(const struct nvkm_subdev *,
+ enum nvkm_falconidx);
+void nvkm_falcon_put(struct nvkm_falcon *falcon);
+
+static inline u32
+nvkm_falcon_rd32(struct nvkm_falcon *falcon, u32 addr)
+{
+ return nvkm_rd32(falcon->subdev->device, falcon-...
2016 Dec 06
9
[PATCH 0/8] Falcon library
This was the first step of the secure boot refactoring - as Ben asked for some
fixes, I now submit it as its own series to make it easier to review (and also
because rebasing secure boot on top of this takes time and I don't want to do
it until this is validated!).
This series attempts to factorize the duplicate falcon-related code into a
single library, using the existing nvkm_falcon
2016 Dec 13
15
[PATCH v2 0/15] Falcon library
This was the first step of the secure boot refactoring - as Ben asked for some
fixes, I now submit it as its own series to make it easier to review (and also
because rebasing secure boot on top of this takes time and I don't want to do
it until this is validated!).
This series attempts to factorize the duplicate falcon-related code into a
single library, using the existing nvkm_falcon
2018 Jan 26
6
[RFC v3 0/4] Implement full clockgating for Kepler1 and 2
Next version of my patchseries for adding clockgating support for
kepler1 and 2 on nouveau. The first version of this series can be found
here:
https://patchwork.freedesktop.org/series/36504/
Some very important changes:
- Fix gf100_clkgate_init() to actually write registers! This got broken
in the last version by accident
- Dump the register packs and the resulting register writes into
2018 Jan 29
5
[RFC v4 0/5] Implement full clockgating for Kepler1 and 2
Next version of my patchseries for adding clockgating support for
kepler1 and 2 on nouveau. The first version of this series can be found
here:
https://patchwork.freedesktop.org/series/36504/
One small change:
- Set therm->clkgate_enabled to false until the last patch, where we
introduce the NvPmEnableGating option
Lyude Paul (5):
drm/nouveau: Add support for basic clockgating on
2018 Jan 30
5
[RFC v5 0/5] Implement full clockgating for Kepler1 and 2
Next version of my patchseries for adding clockgating support for
kepler1 and 2 on nouveau. The first version of this series can be found
here:
https://patchwork.freedesktop.org/series/36504/
One small change:
- Add Martin's R-B, whoops
Lyude Paul (5):
drm/nouveau: Add support for basic clockgating on Kepler1
drm/nouveau: Add support for BLCG on Kepler1
drm/nouveau: Add support for
2018 Feb 01
5
[RFC v6 0/5] Implement full clockgating for Kepler1 and 2
Next version of my patchseries for adding clockgating support for
kepler1 and 2 on nouveau. The first version of this series can be found
here:
https://patchwork.freedesktop.org/series/36504/
Some small changes (shouldn't change anything functionally):
- Made gf100_therm_new, gk104_clkgate_pack, and
gk110_fb_clkgate_blcg_init_unk_0 static (re: kbuild test bot)
- Making all three of
2018 Jan 26
6
[RFC v2 0/4] Implement full clockgating for Kepler1 and 2
Next version of my patchseries for adding clockgating support for
kepler1 and 2 on nouveau. The first version of this series can be found
here:
https://patchwork.freedesktop.org/series/36504/
Some minor changes:
- Clarified that SLCG stands for 'secondary level clockgating', thanks
for the small tip nvidia!
- Removed the concept of levels, this was more useful for debugging
then
2018 Jan 15
6
[RFC 0/4] Implement full clockgating for Kepler1 and 2
It's here! After a lot of investigation, rewrites, and traces, I present
the patch series to implement all known levels of clockgating for
Kepler1 and Kepler2 GPUs.
Starting with Fermi GPUs (this is probably present on earlier GPUs as
well, but with a far less easy to manage interface), nvidia added two
clockgating levels that are handled mostly in firmware (with the
exception of course, of
2016 Oct 11
10
[PATCH 0/8] Secure Boot refactoring
Hi everyone,
Apologies for the big patchset. This is a rework of the secure boot code that
moves the building of the blob into its own set of source files (and own hooks),
making the code more flexible and (hopefully) easier to understand as well.
This rework is needed to support more signed firmware for existing and new
chips. Since the firmwares in question are not available yet I cannot send
2016 Oct 27
15
[PATCH v2 00/14] Secure Boot refactoring
This is a rework of the secure boot code that moves the building of the blob
into its own set of source files (and own hooks), making the code more flexible
and (hopefully) easier to understand as well.
This rework is needed to support more signed firmware for existing and new
chips. Since the firmwares in question are not available yet I cannot send the
code to manage then, but hopefully the
2016 Nov 02
15
[PATCH v3 00/15] Secure Boot refactoring
This is a rework of the secure boot code that moves the building of the blob
into its own set of source files (and own hooks), making the code more flexible
and (hopefully) easier to understand as well.
This rework is needed to support more signed firmware for existing and new
chips. Since the firmwares in question are not available yet I cannot send the
code to manage then, but hopefully the
2016 Nov 21
33
[PATCH v4 0/33] Secure Boot refactoring / signed PMU firmware support for GM20B
This revision includes initial signed PMU firmware support for GM20B
(Tegra X1). This PMU code will also be used as a basis for dGPU signed
PMU firmware support.
With the PMU code, the refactoring of secure boot should also make
more sense.
ACR (secure boot) support is now separated by the driver version it
originates from. This separation allows to run any version of the ACR
on any chip,