search for: nvkm_oclass

Second version of this patchset. Not many changes since first version - I hope this means the changes are not too controversial. Changes since v1: - Removed lookup for previous FW files in "nouveau/" - Went back to using request_firmware() since we only try to load one file Original cover letter follows: GM20B is the GPU of the upcoming Tegra X1 SoC. This series adds initial support

Hello everyone, GM20B is the GPU of the upcoming Tegra X1 SoC. This series adds initial support for it, based on a rework of the already-supported GK20A. It also introduces support for NVIDIA-provided firmware files, which is why I have added a few NVIDIA people who are relevant to this discussion. The first patch adds support for loading the FECS and GPCCS firmwares from firmware files

...2, + .wr32 = nvkm_fifo_chan_mem_wr32, + .sclass = nvkm_fifo_chan_child_get, +}; + int -nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, - struct nvkm_fifo *fifo, u32 size, u32 align, bool zero, - u64 hvmm, u64 push, u64 engines, int bar, u32 base, - u32 user, const struct nvkm_oclass *oclass, - struct nvkm_fifo_chan *chan) +__nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, + struct nvkm_fifo *fifo, u32 size, u32 align, bool zero, + u64 hvmm, u64 push, u64 engines, + const struct nvkm_oclass *oclass, + struct nvkm_fifo_chan *chan) {...

.../instmem/gk20a.c diff --git a/drm/nouveau/include/nvkm/subdev/instmem.h b/drm/nouveau/include/nvkm/subdev/instmem.h index d104c1a..1bcb763 100644 --- a/drm/nouveau/include/nvkm/subdev/instmem.h +++ b/drm/nouveau/include/nvkm/subdev/instmem.h @@ -45,4 +45,5 @@ nvkm_instmem(void *obj) extern struct nvkm_oclass *nv04_instmem_oclass; extern struct nvkm_oclass *nv40_instmem_oclass; extern struct nvkm_oclass *nv50_instmem_oclass; +extern struct nvkm_oclass *gk20a_instmem_oclass; #endif diff --git a/drm/nouveau/nvkm/engine/device/gk104.c b/drm/nouveau/nvkm/engine/device/gk104.c index bf58934..8f266a9 10064...

Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to, and can trick

Changes since v3: - Use a single dma_attr for all DMA-API allocations in instmem instead of one per allocation - Use device.info.ram_size instead of pfb->ram to check whether VRAM is present outside of nvkm Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into

A series I have waited too long to submit, and the recent refactoring made me pay the price of my perfectionism, so here are the features that are at least completed Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to,

Thanks Ilia for the v2 review! Here is the v3 of this IOMMU support for GK20A series. Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove

...nstmem_priv *priv = (void *)nvkm_instmem(node); + + if (priv->domain) + gk20a_instobj_dtor_iommu(node); + else + gk20a_instobj_dtor_dma(node); nvkm_instobj_destroy(&node->base); } static int -gk20a_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 _size, - struct nvkm_object **pobject) +gk20a_instobj_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, u32 npages, u32 align, + struct gk20a_instobj_priv **_node) { - struct nvkm_instobj_args *args = data; +...

...user.h b/drm/nouveau/nvkm/engine/dma/user.h index 69a7f103..1341894b 100644 --- a/drm/nouveau/nvkm/engine/dma/user.h +++ b/drm/nouveau/nvkm/engine/dma/user.h @@ -4,7 +4,7 @@ #include "priv.h" int nvkm_dmaobj_ctor(const struct nvkm_dmaobj_func *, struct nvkm_dma *, - const struct nvkm_oclass *, void **data, u32 *size, + const struct nvkm_oclass *, void **pdata, u32 *psize, struct nvkm_dmaobj *); int nv04_dmaobj_new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32, diff --git a/drm/nouveau/nvkm/subdev/clk/pll.h b/drm/nouveau/nvkm/subdev/clk/pll.h index 44020a3...

...107.c +++ b/drm/nouveau/nvkm/subdev/fuse/gm107.c @@ -45,10 +45,8 @@ gm107_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, ret = nvkm_fuse_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); - if (ret) - return ret; - return 0; + return ret; } struct nvkm_oclass -- 2.2.2

...r warning: drivers/gpu/drm/nouveau/nvkm/core/object.c:298 nvkm_object_ctor() warn: 'object->engine' is an error pointer or valid drivers/gpu/drm/nouveau/nvkm/core/object.c 283 void 284 nvkm_object_ctor(const struct nvkm_object_func *func, 285 const struct nvkm_oclass *oclass, struct nvkm_object *object) 286 { 287 object->func = func; 288 object->client = oclass->client; 289 object->engine = nvkm_engine_ref(oclass->engine); 290 object->oclass = oclass->base.oclass; 291 object-&g...

This fixes a crash when multiple PM engine contexts are created. Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> Reviewed-by: Martin Peres <martin.peres at free.fr> --- drm/nouveau/nvkm/engine/pm/base.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drm/nouveau/nvkm/engine/pm/base.c b/drm/nouveau/nvkm/engine/pm/base.c index 2006c44..274457c

Hi there, Resending these now that they've had some more polish and testing, and I heard that Ben's vacation is over :-) These patches work as a starting point for more explicit error mechanisms and better robustness. At the moment, when a job hangs or faults, it seems that nouveau doesn't quite know how to handle the situation and often results in a hang. Some of these situations

...a/drm/nouveau/nvkm/subdev/devinit/nv50.h b/drm/nouveau/nvkm/subdev/devinit/nv50.h index 5de70a8..25d2ae3 100644 --- a/drm/nouveau/nvkm/subdev/devinit/nv50.h +++ b/drm/nouveau/nvkm/subdev/devinit/nv50.h @@ -20,6 +20,7 @@ int gf100_devinit_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, void *, u32, struct nvkm_object **); int gf100_devinit_pll_set(struct nvkm_devinit *, u32, u32); +void gf100_devinit_preinit(struct nvkm_devinit *); u64 gm107_devinit_disable(struct nvkm_devinit *); #endif -- 2.7.1

Hi, Generally the the imported buffers which has memory type TTM_PL_TT are mapped as small pages probably due to lack of big page allocation. But the platform device which also use memory type TTM_PL_TT, like GK20A, can *allocate* big page though the IOMMU hardware inside the SoC. This is a try to map the imported buffers as big pages in GMMU by the platform IOMMU. With some preparation work to

Hello, This series exposes global performance counters (PCOUNTER) to the userspace through the nvif interface by reworking most of the code related to the PM engine. This interface will allow the userspace to control and monitor complex hardware events like the proprietary driver already does, for example with CUPTI and PerfKit. For now, this series only exposes performance counters on NV50,

This is an initial series of patches to improve channel recovery on Turing GPUs with the goal of improving reliability enough to eventually enable SVM for Turing. It's likely follow up patches will be required to fully address problems with less trivial workloads than what I have been able to test thus far. This series primarily addresses a number of hardware changes to interrupt layout and

...-71,7 +71,7 @@ nvkm_perfdom_find(struct nvkm_pm *pm, int di) return NULL; } -struct nvkm_perfsig * +static struct nvkm_perfsig * nvkm_perfsig_find(struct nvkm_pm *pm, u8 di, u8 si, struct nvkm_perfdom **pdom) { struct nvkm_perfdom *dom = *pdom; @@ -699,7 +699,7 @@ nvkm_pm_oclass_get(struct nvkm_oclass *oclass, int index, return 1; } -int +static int nvkm_perfsrc_new(struct nvkm_pm *pm, struct nvkm_perfsig *sig, const struct nvkm_specsrc *spec) { -- 2.7.4

...-71,7 +71,7 @@ nvkm_perfdom_find(struct nvkm_pm *pm, int di) return NULL; } -struct nvkm_perfsig * +static struct nvkm_perfsig * nvkm_perfsig_find(struct nvkm_pm *pm, u8 di, u8 si, struct nvkm_perfdom **pdom) { struct nvkm_perfdom *dom = *pdom; @@ -699,7 +699,7 @@ nvkm_pm_oclass_get(struct nvkm_oclass *oclass, int index, return 1; } -int +static int nvkm_perfsrc_new(struct nvkm_pm *pm, struct nvkm_perfsig *sig, const struct nvkm_specsrc *spec) { -- 2.7.4