Displaying 20 results from an estimated 143 matches for "nvkm_rd32".
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nv_rd32
2020 Oct 13
3
[PATCH] drm/nouveau/device: fix changing endianess code to work on older GPUs
...evice/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -2924,17 +2924,34 @@ nvkm_device_del(struct nvkm_device **pdevice)
}
}
+/* returns true if the GPU is in the CPU native byte order */
static inline bool
nvkm_device_endianness(struct nvkm_device *device)
{
- u32 boot1 = nvkm_rd32(device, 0x000004) & 0x01000001;
#ifdef __BIG_ENDIAN
- if (!boot1)
- return false;
+ const bool big_endian = true;
#else
- if (boot1)
- return false;
+ const bool big_endian = false;
#endif
+
+ /* Read NV_PMC_BOOT_1, and assume non-functional endian switch if it
+ * doesn't contain the...
2016 Jan 02
0
[PATCH] gr/gf100: provide a bit more info for various errors
...ARED_CONFIG_TOO_SMALL" },
{ 0x04000000, "TOTAL_REGISTER_COUNT" },
{}
@@ -1035,12 +1071,16 @@ gf100_gr_trap_intr(struct gf100_gr *gr)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
+ char error[128];
u32 trap = nvkm_rd32(device, 0x400108);
int rop, gpc;
if (trap & 0x00000001) {
u32 stat = nvkm_rd32(device, 0x404000);
- nvkm_error(subdev, "DISPATCH %08x\n", stat);
+
+ nvkm_snprintbf(error, sizeof(error), gf100_dispatch_error,
+ stat & 0x3fffffff);
+ nvkm_error(subdev, "DIS...
2016 Jan 02
0
[PATCH v2] gr/gf100: provide a bit more info for various errors
...ARED_CONFIG_TOO_SMALL" },
{ 0x04000000, "TOTAL_REGISTER_COUNT" },
{}
@@ -1035,12 +1071,16 @@ gf100_gr_trap_intr(struct gf100_gr *gr)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
+ char error[128];
u32 trap = nvkm_rd32(device, 0x400108);
int rop, gpc;
if (trap & 0x00000001) {
u32 stat = nvkm_rd32(device, 0x404000);
- nvkm_error(subdev, "DISPATCH %08x\n", stat);
+
+ nvkm_snprintbf(error, sizeof(error), gf100_dispatch_error,
+ stat & 0x3fffffff);
+ nvkm_error(subdev, "DIS...
2017 Oct 08
1
[RFC PATCH 03/29] subdev/volt/gk104: return error when read fails
On 2017-09-15 — 17:11, Karol Herbst wrote:
> While my gpu was powered off, hwmon returned 0.6V as the current voltage.
> If nvkm_rd32 fails for any reason, return the error.
>
> With that sensors will display a "N/A" instead of 0.6V.
Small nitpick, add a comma between “that” and “sensors”.
Otherwise,
Reviewed-by: Pierre Moreau <pierre.morrow at free.fr>
>
> Signed-off-by: Karol Herbst <karolher...
2020 Oct 13
0
[PATCH] drm/nouveau/device: fix changing endianess code to work on older GPUs
...device/base.c
> @@ -2924,17 +2924,34 @@ nvkm_device_del(struct nvkm_device **pdevice)
> }
> }
>
> +/* returns true if the GPU is in the CPU native byte order */
> static inline bool
> nvkm_device_endianness(struct nvkm_device *device)
> {
> - u32 boot1 = nvkm_rd32(device, 0x000004) & 0x01000001;
> #ifdef __BIG_ENDIAN
> - if (!boot1)
> - return false;
> + const bool big_endian = true;
> #else
> - if (boot1)
> - return false;
> + const bool big_endian = false;
> #endif
> +...
2015 Nov 14
2
[PATCH v2] pmu: use nvkm_msec instead of do while
...3..eb248fd 100644
--- a/drm/nouveau/nvkm/subdev/pmu/base.c
+++ b/drm/nouveau/nvkm/subdev/pmu/base.c
@@ -100,9 +100,16 @@ nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2],
}
/* acquire data segment access */
- do {
+ nvkm_wr32(device, 0x10a580, 0x00000001);
+ if (nvkm_msec(device, 2000,
+ if (nvkm_rd32(device, 0x10a580) == 0x00000001)
+ break;
nvkm_wr32(device, 0x10a580, 0x00000001);
- } while (nvkm_rd32(device, 0x10a580) != 0x00000001);
+ ) < 0) {
+ if (reply)
+ mutex_unlock(&subdev->mutex);
+ return -EBUSY;
+ }
/* write the packet */
nvkm_wr32(device, 0x10a1c0, 0x010000...
2017 Jul 03
2
[PATCH] disp/gf119-: avoid creating non-existent heads
.../engine/disp/gf119.c
index d8765b57..415987e9 100644
--- a/drm/nouveau/nvkm/engine/disp/gf119.c
+++ b/drm/nouveau/nvkm/engine/disp/gf119.c
@@ -168,7 +168,7 @@ int
gf119_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device,
int index, struct nvkm_disp **pdisp)
{
- u32 heads = nvkm_rd32(device, 0x022448);
+ u32 heads = fls(nvkm_rd32(device, 0x612004) & 0xf);
return nv50_disp_new_(func, device, index, heads, pdisp);
}
diff --git a/drm/nouveau/nvkm/engine/disp/headgf119.c b/drm/nouveau/nvkm/engine/disp/headgf119.c
index b3355275..8d44bdf6 100644
--- a/drm/nouveau/nvkm/engin...
2019 Sep 06
1
[PATCH v3] clk: Restore BYPASS_PLL_CHECK from PLLs
...7) {
nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000);
nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000);
@@ -376,12 +377,14 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx)
nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
/* Test PLL lock */
+ bypass_state = nvkm_rd32(device, addr + 0x00) & 0x00000010;
nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000);
nvkm_msec(device, 2000,
if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
break;
);
- nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010);
+ if (bypass_state)
+ nvkm_ma...
2016 Jun 17
1
[PATCH v2 1/2] nvkm/clk/gf100+: Clean up PLL locking test
...lk_prog_2(struct gf100_clk *clk, int idx)
if (info->coef) {
nvkm_wr32(device, addr + 0x04, info->coef);
nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
+
+ /* Test PLL lock */
+ nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000);
nvkm_msec(device, 2000,
if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
break;
);
- nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004);
+ nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010);
+
+ /* Enable sync mode */
+ nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004);
}
}
}
diff --git a/driver...
2016 Jun 01
15
[PATCH 00/15] clk/tegra: improve code and add DFS support
This series adds support for GM20B PLL's Maxwell features, namely glitchless
switch and (more importantly) DFS support. DFS lets the PLL lower its output
speed according to input current variations, making the clock more stable and
allowing it to run safely at lower voltage.
All GM20B additions are done in the last patch, which consequently ends up
being considerably big ; fortunately, it
2017 Apr 10
0
[PATCH 08/11] nvkm/ramgt215: Add train ptrn upload for GDDR5
...r32(device, 0x100538, 0x10000000 | (mem->offset >> 16));
nvkm_wr32(device, 0x1005a8, 0x0000ffff);
@@ -388,17 +424,50 @@ gt215_link_train_init(struct gt215_ram *ram)
nvkm_wr32(device, 0x700100 + (i << 2), pattern[i]);
nvkm_wr32(device, 0x1700, r001700);
- train->r_100720 = nvkm_rd32(device, 0x100720);
- train->r_1111e0 = nvkm_rd32(device, 0x1111e0);
- train->r_111400 = nvkm_rd32(device, 0x111400);
+ train_ddr3->r_100720 = nvkm_rd32(device, 0x100720);
+ train_ddr3->r_1111e0 = nvkm_rd32(device, 0x1111e0);
+ train_ddr3->r_111400 = nvkm_rd32(device, 0x111400);
ret...
2016 Mar 01
2
[PATCH 0/2] PMU communications improvements
Both patches should make the communicating with the PMU more stable.
Karol Herbst (2):
pmu: fix queued messages while getting no IRQ
pmu: be more strict about locking
drm/nouveau/nvkm/subdev/pmu/base.c | 49 ++++++++++++++++++++++++++++++++------
1 file changed, 42 insertions(+), 7 deletions(-)
--
2.7.2
2015 Nov 16
1
[PATCH] fifo/gk104: fix engine status register offset
...00644
--- a/drm/nouveau/nvkm/engine/fifo/gk104.c
+++ b/drm/nouveau/nvkm/engine/fifo/gk104.c
@@ -196,7 +196,7 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo)
spin_lock_irqsave(&fifo->base.lock, flags);
for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) {
- u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04));
+ u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08));
u32 busy = (stat & 0x80000000);
u32 next = (stat & 0x07ff0000) >> 16;
u32 chsw = (stat & 0x00008000);
--
2.1.4
2020 Aug 24
2
nouveau PUSHBUFFER_ERR on 5.9.0-rc2-next-20200824
...isp/nv50.c:613,645.
And nv50_disp_intr_error is called from nv50_disp_intr in the
following while block:
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c:647,658
void
nv50_disp_intr(struct nv50_disp *disp)
{
struct nvkm_device *device = disp->base.engine.subdev.device;
u32 intr0 = nvkm_rd32(device, 0x610020);
u32 intr1 = nvkm_rd32(device, 0x610024);
while (intr0 & 0x001f0000) {
u32 chid = __ffs(intr0 & 0x001f0000) - 16;
nv50_disp_intr_error(disp, chid);
intr0 &= ~(0x00010000 << chid);
}
...
}
C...
2016 Jun 04
3
PM + Init work
Following a series of three patches, two of which have been sitting in my tree
for a while, the third is the result of some inspection of an NV134 BIOS that
seems to use the 0xaf upcode to upload training patterns. Please test!
Roy
Ps. Sorry they come from yet another e-mail address. My previous provider,
eclipso, actively blocks users of git send-email. Inquiries fall on deaf
ears, hence I
2017 Mar 29
0
[PATCH 12/15] gr: support for GP10B
...6 +40,15 @@ gp100_gr_init_rop_active_fbps(struct gf100_gr *gr)
nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
}
+void
+gp100_gr_init_num_active_ltcs(struct gf100_gr *gr)
+{
+ struct nvkm_device *device = gr->base.engine.subdev.device;
+
+ nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
+ nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804));
+}
+
int
gp100_gr_init(struct gf100_gr *gr)
{
@@ -81,8 +90,7 @@ gp100_gr_init(struct gf100_gr *gr)
}
nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
- nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(...
2019 Sep 04
1
[RFC PATCH v2] clk: Remove BYPASS_PLL_CHECK from PLLs
...d, 2 deletions(-)
diff --git a/drm/nouveau/nvkm/subdev/clk/gf100.c b/drm/nouveau/nvkm/subdev/clk/gf100.c
index 7f67f9f5..fe56817b 100644
--- a/drm/nouveau/nvkm/subdev/clk/gf100.c
+++ b/drm/nouveau/nvkm/subdev/clk/gf100.c
@@ -381,7 +381,6 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx)
if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
break;
);
- nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010);
/* Enable sync mode */
nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004);
diff --git a/drm/nouveau/nvkm/subdev/clk/gk104.c b/drm/nouveau/nvkm/subdev/clk/gk104.c
inde...
2020 Oct 30
6
[PATCH 0/5] Improve Robust Channel (RC) recovery for Turing
This is an initial series of patches to improve channel recovery on Turing GPUs
with the goal of improving reliability enough to eventually enable SVM for
Turing. It's likely follow up patches will be required to fully address problems
with less trivial workloads than what I have been able to test thus far.
This series primarily addresses a number of hardware changes to interrupt layout
and
2017 Aug 06
1
[PATCH] drm/nouveau/mpeg: print more debug info when rejecting dma objects
...ct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile)
static bool
nv31_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
{
+ struct nv31_mpeg *mpeg = nv31_mpeg(device->mpeg);
+ struct nvkm_subdev *subdev = &mpeg->engine.subdev;
u32 inst = data << 4;
u32 dma0 = nvkm_rd32(device, 0x700000 + inst);
u32 dma1 = nvkm_rd32(device, 0x700004 + inst);
@@ -132,8 +134,11 @@ nv31_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
u32 size = dma1 + 1;
/* only allow linear DMA objects */
- if (!(dma0 & 0x00002000))
+ if (!(dma0 & 0x00002000)) {
+ nvkm...
2016 Jun 04
0
[PATCH 2/3] nvkm/clk/gf100: Read secondary bypass postdiv when required
...f100.c
index f9a4918..80c6dd6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
@@ -99,7 +99,7 @@ read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
{
struct nvkm_device *device = clk->base.subdev.device;
u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4));
- u32 sctl = nvkm_rd32(device, dctl + (doff * 4));
+ u32 sclk, sctl, sdiv = 2;
switch (ssrc & 0x00000003) {
case 0:
@@ -109,13 +109,21 @@ read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
case 2:
return 100000;
case 3:
- if (sctl & 0x800...