Displaying 20 results from an estimated 171 matches for "nv_rd32".
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__rd32
2010 Mar 01
0
[PATCH 2/2 V2] drm/nv50: Improve PGRAPH interrupt handling.
...08x:0x%08x\n",
@@ -578,27 +605,502 @@ nouveau_pgraph_irq_handler(struct drm_device *dev)
}
static void
+nv50_pfb_vm_trap(struct drm_device *dev, int display, const char *name)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ uint32_t trap[6];
+ int i, ch;
+ uint32_t idx = nv_rd32(dev, 0x100c90);
+ if (idx & 0x80000000) {
+ idx &= 0xffffff;
+ if (display) {
+ for (i = 0; i < 6; i++) {
+ nv_wr32(dev, 0x100c90, idx | i << 24);
+ trap[i] = nv_rd32(dev, 0x100c94);
+ }
+ for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) {
+ struct nou...
2012 Dec 09
0
[PATCH 1/4] drm/nouveau: split fifo interrupt handler
...ctually goes to 0xffc before wrapping on my
+ * G80 chips, but CACHE1 isn't big enough for this much data.. Tests
+ * show that it wraps around to the start at GET=0x800.. No clue as to
+ * why..
+ */
+ ptr = (get & 0x7ff) >> 2;
+
+ if (device->card_type < NV_40) {
+ mthd = nv_rd32(priv, NV04_PFIFO_CACHE1_METHOD(ptr));
+ data = nv_rd32(priv, NV04_PFIFO_CACHE1_DATA(ptr));
+ } else {
+ mthd = nv_rd32(priv, NV40_PFIFO_CACHE1_METHOD(ptr));
+ data = nv_rd32(priv, NV40_PFIFO_CACHE1_DATA(ptr));
+ }
+
+ if (!nv04_fifo_swmthd(priv, chid, mthd, data)) {
+ nv_error(priv,
+ "...
2010 Feb 28
1
[PATCH 1/2] drm/nv50: Make ctxprog wait until interrupt handler is done.
This will fix races between generated ctxprogs and interrupt handler.
Signed-off-by: Marcin Ko?cielnicki <koriakin at 0x04.net>
---
drivers/gpu/drm/nouveau/nv50_grctx.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c
index d105fcd..9f909ab 100644
---
2014 Jan 16
2
[PATCH] drm/nv50/graph: add more trap names to print on error
...t; },
+ { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" },
+ { 0x00000800, "DST2D_LINEAR_MISMATCH" },
+ { 0x00001000, "RT_LINEAR_MISMATCH" },
+ {}
+};
+
+static u32
+nv50_priv_prop_trap(struct nv50_graph_priv *priv,
+ u32 ustatus_addr, u32 ustatus, u32 tp)
+{
+ u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
+ u32 e10 = nv_rd32(priv, ustatus_addr + 0x08);
+ u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c);
+ u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
+ u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
+ u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
+ u32 e24 = nv_rd32(priv, ustat...
2012 Nov 06
1
[PATCH] drm/nv50: decode PGRAPH status registers on TLB flush fail
...ne *engine)
{
@@ -219,10 +275,21 @@ nv84_graph_tlb_flush(struct nouveau_engine *engine)
!(timeout = ptimer->read(ptimer) - start > 2000000000));
if (timeout) {
- nv_error(priv, "PGRAPH TLB flush idle timeout fail: "
- "0x%08x 0x%08x 0x%08x 0x%08x\n",
- nv_rd32(priv, 0x400700), nv_rd32(priv, 0x400380),
- nv_rd32(priv, 0x400384), nv_rd32(priv, 0x400388));
+ nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");
+
+ nv_error(priv, "PGRAPH_STATUS: ");
+ tmp = nv_rd32(priv, 0x400700);
+ nouveau_bitfield_print(nv50_pgraph_status, tm...
2012 Aug 19
1
[PATCH 01/10] drm/nv50: decode PGRAPH status registers on TLB flush fail
...ne *engine)
{
@@ -219,10 +275,24 @@ nv84_graph_tlb_flush(struct nouveau_engine *engine)
!(timeout = ptimer->read(ptimer) - start > 2000000000));
if (timeout) {
- nv_error(priv, "PGRAPH TLB flush idle timeout fail: "
- "0x%08x 0x%08x 0x%08x 0x%08x\n",
- nv_rd32(priv, 0x400700), nv_rd32(priv, 0x400380),
- nv_rd32(priv, 0x400384), nv_rd32(priv, 0x400388));
+ nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");
+
+ nv_error(priv, "PGRAPH_STATUS: ");
+ tmp = nv_rd32(priv, 0x400700);
+ nouveau_bitfield_print(nv50_pgraph_status, tm...
2014 Jan 16
0
[PATCH] drm/nv50/graph: add more trap names to print on error
..., "DST2D_LINEAR_MISMATCH" },
> + { 0x00001000, "RT_LINEAR_MISMATCH" },
> + {}
> +};
> +
> +static u32
> +nv50_priv_prop_trap(struct nv50_graph_priv *priv,
> + u32 ustatus_addr, u32 ustatus, u32 tp)
> +{
> + u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
> + u32 e10 = nv_rd32(priv, ustatus_addr + 0x08);
> + u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c);
> + u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
> + u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
> + u32 e20 = nv_rd32(priv...
2013 Jul 30
0
[PATCH] drm/nv50-/disp: use the number of dac, sor, pior rather than hardcoded values
...100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -628,7 +628,7 @@ nv50_disp_base_init(struct nouveau_object *object)
}
/* ... PIOR caps */
- for (i = 0; i < 3; i++) {
+ for (i = 0; i < priv->pior.nr; i++) {
tmp = nv_rd32(priv, 0x61e000 + (i * 0x800));
nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp);
}
@@ -834,10 +834,11 @@ exec_script(struct nv50_disp_priv *priv, int head, int id)
u8 ver, hdr, cnt, len;
u16 data;
u32 ctrl = 0x00000000;
+ u32 reg;
int i;
/* DAC */
- for (i = 0; !(ctrl & (1 << h...
2009 Dec 11
5
[PATCH 1/3] drm/nouveau: Pre-G80 tiling support.
..._nouveau_private *dev_priv = dev->dev_private;
@@ -836,17 +869,9 @@ int nv10_graph_init(struct drm_device *dev)
} else
nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000);
- /* copy tile info from PFB */
- for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
- nv_wr32(dev, NV10_PGRAPH_TILE(i),
- nv_rd32(dev, NV10_PFB_TILE(i)));
- nv_wr32(dev, NV10_PGRAPH_TLIMIT(i),
- nv_rd32(dev, NV10_PFB_TLIMIT(i)));
- nv_wr32(dev, NV10_PGRAPH_TSIZE(i),
- nv_rd32(dev, NV10_PFB_TSIZE(i)));
- nv_wr32(dev, NV10_PGRAPH_TSTATUS(i),
- nv_rd32(dev, NV10_PFB_TSTATUS(i)));
- }
+ /* Turn all the tiling regio...
2014 Apr 15
2
[PATCH] drm/nouveau/bios: fix a bit shift error introduced by 457e77b
Commit 457e77b26428ab4a24998eecfb99f27fa4195397 added two checks applied to a
value received from nv_rd32(bios, 0x619f04). But after this new piece of code
is executed, the addr local variable does not hold the same value it used to
hold before the commit. Here is what is was assigned in the original code:
(u64)(nv_rd32(bios, 0x619f04) & 0xffffff00) << 8
in the committed code it ends up with...
2013 Aug 09
0
[PATCH] drm/nouveau/fb: fix null derefs in nv49 and nv4e init
...e 0x00000002: pfb->ram->type = NV_MEM_TYPE_GDDR3; break;
+ case 0x00000000: ram->type = NV_MEM_TYPE_DDR1; break;
+ case 0x00000001: ram->type = NV_MEM_TYPE_DDR2; break;
+ case 0x00000002: ram->type = NV_MEM_TYPE_GDDR3; break;
case 0x00000003: break;
}
- pfb->ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
- pfb->ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
- pfb->ram->tags = nv_rd32(pfb, 0x100320);
+ ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
+ ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
+ ram->tags =...
2015 Mar 11
0
[PATCH] pmu/gk20a: PMU boot support.
...ize & 0x3;
> +
> + addr_mask = (0x3f << 2) | 0xff << 8;
> +
> + src &= addr_mask;
> +
> + nv_wr32(ppmu, (0x10a1c0 + (port * 8)), (src | (0x1 << 25)));
> +
> + for (i = 0; i < words; i++) {
> + dst_u32[i] = nv_rd32(ppmu, (0x0010a1c4 + port * 8));
> + nv_debug(ppmu, "0x%08x\n", dst_u32[i]);
> + }
> + if (bytes > 0) {
> + data = nv_rd32(ppmu, (0x0010a1c4 + port * 8));
> + nv_debug(ppmu, "0x%08x\n", data);
> +
> +...
2013 Mar 27
3
[PATCH 1/4] drm/nvc0: implement VRAM compression
...struct nvc0_ltcg_priv *priv;
+ struct nouveau_fb *pfb = nouveau_fb(parent);
int ret;
ret = nouveau_ltcg_create(parent, engine, oclass, &priv);
@@ -74,19 +174,44 @@ nvc0_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret)
return ret;
- priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 24;
+ priv->part_nr = nv_rd32(priv, 0x022438);
+ priv->part_mask = nv_rd32(priv, 0x022554);
+
+ priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28;
+
nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
+ ret = nvc0_ltcg_init_tag_ram(pfb...
2014 Mar 25
2
[PATCH 4/4] vbios/prom: fetch the vbios using only aligned 32-bit accesses
...ound for a PROM reading
* issue on some chipsets. the first read after a period of
* inactivity returns the wrong result, so retry the first header
@@ -164,31 +168,38 @@ nouveau_bios_shadow_prom(struct nouveau_bios *bios)
*/
i = 16;
do {
- if (nv_rd08(bios, 0x300000) == 0x55)
+ if ((nv_rd32(bios, 0x300000) & 0xffff) == 0xaa55)
break;
} while (i--);
- if (!i || nv_rd08(bios, 0x300001) != 0xaa)
+ if (!i)
goto out;
- /* additional check (see note below) - read PCI record header */
- pcir = nv_rd08(bios, 0x300018) |
- nv_rd08(bios, 0x300019) << 8;
- if (nv_rd...
2015 Mar 11
3
[PATCH] pmu/gk20a: PMU boot support.
...+ mutex_lock(&pmu->pmu_copy_lock);
+
+ words = size >> 2;
+ bytes = size & 0x3;
+
+ addr_mask = (0x3f << 2) | 0xff << 8;
+
+ src &= addr_mask;
+
+ nv_wr32(ppmu, (0x10a1c0 + (port * 8)), (src | (0x1 << 25)));
+
+ for (i = 0; i < words; i++) {
+ dst_u32[i] = nv_rd32(ppmu, (0x0010a1c4 + port * 8));
+ nv_debug(ppmu, "0x%08x\n", dst_u32[i]);
+ }
+ if (bytes > 0) {
+ data = nv_rd32(ppmu, (0x0010a1c4 + port * 8));
+ nv_debug(ppmu, "0x%08x\n", data);
+
+ for (i = 0; i < bytes; i++)
+ dst[(words << 2) + i] = ((u8 *)&data)[i];...
2015 Mar 12
2
[PATCH] pmu/gk20a: PMU boot support.
...ize & 0x3;
> +
> + addr_mask = (0x3f << 2) | 0xff << 8;
> +
> + src &= addr_mask;
> +
> + nv_wr32(ppmu, (0x10a1c0 + (port * 8)), (src | (0x1 << 25)));
> +
> + for (i = 0; i < words; i++) {
> + dst_u32[i] = nv_rd32(ppmu, (0x0010a1c4 + port * 8));
> + nv_debug(ppmu, "0x%08x\n", dst_u32[i]);
> + }
> + if (bytes > 0) {
> + data = nv_rd32(ppmu, (0x0010a1c4 + port * 8));
> + nv_debug(ppmu, "0x%08x\n", data);
> +
> +...
2009 Sep 06
2
[PATCH 1/4] drm/nouveau: add reg_debug module parameter
...vers/gpu/drm/nouveau/nouveau_hw.h b/drivers/gpu/drm/nouveau/nouveau_hw.h
index 129345e..a1880c4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hw.h
+++ b/drivers/gpu/drm/nouveau/nouveau_hw.h
@@ -59,14 +59,14 @@ static inline uint32_t
nvReadMC(struct drm_device *dev, uint32_t reg)
{
uint32_t val = nv_rd32(dev, reg);
- NV_DEBUG(dev, "nvReadMC: reg %08x val %08x\n", reg, val);
+ NV_REG_DEBUG(MC, dev, "reg %08x val %08x\n", reg, val);
return val;
}
static inline void
nvWriteMC(struct drm_device *dev, uint32_t reg, uint32_t val)
{
- NV_DEBUG(dev, "nvWriteMC: reg %08x val...
2014 Jan 10
2
[PATCH 1/3] drm/nouveau: provide a way for devinit to mark engines as disabled
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
I decided to let the user still specify config=BLA=1 to override the hw
disable in case we get something wrong or for double-checking stuff, but I
suspect it won't really be used much. I'm not terribly fond of the message
text, if you come up with something better, feel free to drop it in.
2014 Jul 10
0
[PATCH 3/3] drm/gk20a: reclocking support
...iv {
+ struct nouveau_clock base;
+ const struct gk20a_clk_pllg_params *params;
+ u32 m, n, pl;
+ unsigned long parent_rate;
+};
+#define to_gk20a_clock(base) container_of(base, struct gk20a_clock_priv, base)
+
+static void
+gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv)
+{
+ u32 val;
+
+ val = nv_rd32(priv, GPCPLL_COEFF);
+ priv->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
+ priv->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
+ priv->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
+}
+
+static unsigned...
2012 Jun 25
1
[PATCH 1/2] drm/nouveau/pm: Prepare for more GDDR5 MR values
...dt << 2);
+ (t->odt << 2) |
+ (add_term << 4);
NV_DEBUG(ndev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[1]);
return 0;
@@ -783,9 +790,15 @@ nouveau_mem_timing_read(struct nouveau_device *ndev, struct nouveau_pm_memtiming
}
t->mr[0] = nv_rd32(ndev, mr_base);
- t->mr[1] = nv_rd32(ndev, mr_base + 0x04);
- t->mr[2] = nv_rd32(ndev, mr_base + 0x20);
- t->mr[3] = nv_rd32(ndev, mr_base + 0x24);
+ if (pfb->ram.type == NV_MEM_TYPE_GDDR5 &&
+ ndev->card_type >= 0xC0) {
+ for (i = 0; i < 8; i++)
+ t->mr[i+1] = n...