search for: nvkm_pmu_intr

I encountered while stresstesting the reclocking code, that rarely (1 out of 20.000+ requests) we don't get any IRQ in nvkm_pmu_intr. This means we have a queued message on the pmu, but nouveau doesn't read it and waits infinitely in nvkm_pmu_send: if (reply) { wait_event(pmu->recv.wait, (pmu->recv.process == 0)); therefore let us use wait_event_timeout with a 1s timeout frame and just check whether there is a mes...

...data->core = get_counter_index(result[0], 0); > + data->video = get_counter_index(result[0], 1); > + data->mem = get_counter_index(result[0], 2); > + data->pcie = get_counter_index(result[0], 3); > + return 0; > +} > + > static void > nvkm_pmu_intr(struct nvkm_subdev *subdev) > { > -- > 2.6.2 > > _______________________________________________ > Nouveau mailing list > Nouveau at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/nouveau

...iles changed, 17 insertions(+), 6 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/pmu/base.c b/drm/nouveau/nvkm/subdev/pmu/base.c index 1e645eec1951..6db1ee45e610 100644 --- a/drm/nouveau/nvkm/subdev/pmu/base.c +++ b/drm/nouveau/nvkm/subdev/pmu/base.c @@ -128,13 +128,10 @@ nvkm_pmu = { .intr = nvkm_pmu_intr, }; -int -nvkm_pmu_new_(const struct nvkm_pmu_func *func, struct nvkm_device *device, - int index, struct nvkm_pmu **ppmu) +void +nvkm_pmu_ctor(const struct nvkm_pmu_func *func, struct nvkm_device *device, + int index, struct nvkm_pmu *pmu) { - struct nvkm_pmu *pmu; - if (!(pmu = *p...

I encountered while stresstesting the reclocking code, that rarely (1 out of 20.000+ requests) we don't get any IRQ in nvkm_pmu_intr. This means we have a queued message on the pmu, but nouveau doesn't read it and waits infinitely in nvkm_pmu_send: if (reply) { wait_event(pmu->recv.wait, (pmu->recv.process == 0)); therefore let us use wait_event_timeout with a 1s timeout frame and just check whether there is a mes...

I encountered while stresstesting the reclocking code, that rarely (1 out of 20.000+ requests) we don't get any IRQ in nvkm_pmu_intr. This means we have a queued message on the pmu, but nouveau doesn't read it and waits infinitely in nvkm_pmu_send: if (reply) { wait_event(pmu->recv.wait, (pmu->recv.process == 0)); therefore let us use wait_event_timeout with a 1s timeout frame and just check whether there is a mes...

...PERF, PERF_MSG_LOAD, 0, 0); + + if (ret < 0) + return ret; + + data->core = get_counter_index(result[0], 0); + data->video = get_counter_index(result[0], 1); + data->mem = get_counter_index(result[0], 2); + data->pcie = get_counter_index(result[0], 3); + return 0; +} + static void nvkm_pmu_intr(struct nvkm_subdev *subdev) { -- 2.6.2

...PERF, PERF_MSG_LOAD, 0, 0); + + if (ret < 0) + return ret; + + data->core = get_counter_index(result[0], 0); + data->video = get_counter_index(result[0], 1); + data->mem = get_counter_index(result[0], 2); + data->pcie = get_counter_index(result[0], 3); + return 0; +} + static void nvkm_pmu_intr(struct nvkm_subdev *subdev) { -- 2.6.2

...C_PERF, PERF_MSG_LOAD, 0, 0); + if (ret < 0) + return ret; + + data->core = get_counter_index(result[0], 0); + data->video = get_counter_index(result[0], 1); + data->mem = get_counter_index(result[0], 2); + data->pcie = get_counter_index(result[0], 3); + return 0; +} + static void nvkm_pmu_intr(struct nvkm_subdev *subdev) { -- 2.6.2

Both patches should make the communicating with the PMU more stable. Karol Herbst (2): pmu: fix queued messages while getting no IRQ pmu: be more strict about locking drm/nouveau/nvkm/subdev/pmu/base.c | 49 ++++++++++++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 7 deletions(-) -- 2.7.2

this series makes use of the load counters we can use to get information about the current load of the gpu. This series includes the needed pmu bits and a debugfs interface to read them out. Currently the values are between 0 and 255, because it is much easier to implement it this way on the pmu. Karol Herbst (4): subdev/pmu/fuc: add gk104 pmu/fuc: add macros for pdaemon pwr counters

these are usually used for dynamic reclocking on gt215 and newer The counters are used to get the load of the core, memory, video and pcie loads currently I expose the loads through a debugfs "current_load" file, but I want to move that to nvif and just add a wrapper around that in debugfs for convenience Anyway there are still some issues I would like to discuss: 1. currently the

these are usually used for dynamic reclocking on gt215 and newer The counters are used to get the load of the core, memory, video and pcie loads currently I expose the loads through a debugfs "current_load" file, but I want to move that to nvif and just add a wrapper around that in debugfs for convenience. Using nvif would have the advantage, that userspace tools can easily get loads

Changes since last sent: * add a patch to set the device into DRM_SWITCH_POWER_CHANGING state (can be dropped actually, I thought I was needing it, came up with a different approach and forgot to delete it, doesn't hurt though) * expose information about runtime suspending to nvkm so that we can run the pcie workaround only on runtime suspend Karol Herbst (8): pci: disable ASPM

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

reworked this series quite a lot. Now we want the Host to configure the counters through the PMU. The series isn't complete though because it needs: 1. reordering 2. better commit messages but I felt like sending those out before doing a final version. I also found some weird register overwriting issue on the PMU I have to track down, because it interfers with the counter read out. I am

I think I am done reworking the series and getting to a point where I think it is basically finished. The configuration of the slots could be improved later on when working on dynamic reclocking, but for now it's good enough to report the current GPU utilization to userspace. Patches 1-4 imeplement PMU commands to setup and readout the counters. Patches 5-6 lets Nouveau make use of 1-4. Patch

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,