search for: nvkm_mc_intr

...ing the screen. Launching weston or kmscon works, but starting X makes the whole computer freeze (no responce on key presses, power button press, capslock not working). I’ll try to setup netconsole and SSH later to gather some logs. On one of the boots, I got a slow path warning in nvkm_pci_intr()/nvkm_mc_intr(). Trying to suspend the computer simply results in the computer not suspending and freezing. -- You are receiving this mail because: You are the assignee for the bug. -------------- next part -------------- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/nouve...

...eau/nvkm/subdev/mc/base.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/subdev/mc/base.c b/drm/nouveau/nvkm/subdev/mc/base.c index aa394af..88bc1cc 100644 --- a/drm/nouveau/nvkm/subdev/mc/base.c +++ b/drm/nouveau/nvkm/subdev/mc/base.c @@ -90,10 +90,15 @@ nvkm_mc_intr(struct nvkm_mc *mc, bool *handled) void nvkm_mc_reset(struct nvkm_mc *mc, enum nvkm_devidx devidx) { - struct nvkm_device *device = mc->subdev.device; + struct nvkm_device *device; const struct nvkm_mc_map *map; u64 pmc_enable; + if (!mc) + return; + + device = mc->subdev.device; +...

...bdev/mc.h @@ -9,6 +9,7 @@ struct nvkm_mc { void nvkm_mc_enable(struct nvkm_device *, enum nvkm_devidx); void nvkm_mc_disable(struct nvkm_device *, enum nvkm_devidx); +bool nvkm_mc_enabled(struct nvkm_device *, enum nvkm_devidx); void nvkm_mc_reset(struct nvkm_device *, enum nvkm_devidx); void nvkm_mc_intr(struct nvkm_device *, bool *handled); void nvkm_mc_intr_unarm(struct nvkm_device *); diff --git a/drm/nouveau/nvkm/subdev/mc/base.c b/drm/nouveau/nvkm/subdev/mc/base.c index 6b25e25f9eba..09f669ac6630 100644 --- a/drm/nouveau/nvkm/subdev/mc/base.c +++ b/drm/nouveau/nvkm/subdev/mc/base.c @@ -161,6...

On Fri, Nov 24, 2017 at 3:02 PM, Thierry Reding <thierry.reding at gmail.com> wrote: > On Fri, Nov 24, 2017 at 03:56:26AM +0100, Karol Herbst wrote: >> On my GP107 when I load nouveau after unloading it, for some reason the >> GPU stopped sending or the CPU stopped receiving interrupts if MSI was >> enabled. > > I suppose this could happen if the GPU raises an

...appearing once the window is redrawn, then start appearing again. Crash (only one happened so far): [18827.759324] nouveau 0000:01:00.0: fifo: intr 04000000 [18829.968650] ------------[ cut here ]------------ [18830.073628] WARNING: CPU: 1 PID: 0 at drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c:72 nvkm_mc_intr+0x144/0x160 [nouveau] [18830.078080] nouveau 0000:01:00.0: timeout [18830.089198] Modules linked in: arc4 mt7601u mac80211 sha256_generic cfg80211 rfkill nouveau video ttm [18830.093352] WARNING: CPU: 3 PID: 7568 at drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c:38 g84_bar_flush+0xb4/0xc0 [nouveau]...

...c0ac2b8d>] ? _raw_spin_unlock_irqrestore+0xd/0x10 [<f8537d7b>] ? nvkm_event_send+0x9b/0xe0 [nouveau] [<f85960e1>] nvkm_fifo_intr+0x11/0x20 [nouveau] [<f85375f9>] nvkm_engine_intr+0x19/0x20 [nouveau] [<f853b623>] nvkm_subdev_intr+0x13/0x20 [nouveau] [<f8577871>] nvkm_mc_intr+0x61/0xf0 [nouveau] [<c080e2ee>] ? add_interrupt_randomness+0x14e/0x1b0 [<f857bf42>] nvkm_pci_intr+0x42/0x80 [nouveau] [<c04b5006>] handle_irq_event_percpu+0x76/0x190 [<c04b7d60>] ? handle_simple_irq+0x70/0x70 [<c04b514a>] handle_irq_event+0x2a/0x50 [<c04b7dd2...

...nouveau/nvkm/engine/disp/nv50.c:116) nvkm_disp_intr+0x53/0x70 [nouveau] (drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c:204) nvkm_engine_intr+0x57/0x70 [nouveau] (drivers/gpu/drm/nouveau/nvkm/core/engine.c:71) nvkm_subdev_intr+0x54/0x70 [nouveau] (drivers/gpu/drm/nouveau/nvkm/core/subdev.c:88) nvkm_mc_intr+0x23a/0x4b0 [nouveau] (drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c:79) ? nvkm_mc_intr_rearm+0xa0/0xa0 [nouveau] (drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c:62) ? nv40_pci_wr08+0x68/0xa0 [nouveau] (drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c:35) ? nvkm_pci_wr08+0x57/0x90 [nouveau] (driver...

...1:42 dioo-XPS kernel: [ 2185.090575] [<ffffffffc0860266>] nv04_timer_alarm_trigger+0x126/0x170 [nouveau] Jul 21 10:11:42 dioo-XPS kernel: [ 2185.090584] [<ffffffffc08603fb>] nv04_timer_intr+0x6b/0x90 [nouveau] Jul 21 10:11:42 dioo-XPS kernel: [ 2185.090594] [<ffffffffc0856df5>] nvkm_mc_intr+0x105/0x160 [nouveau] Jul 21 10:11:42 dioo-XPS kernel: [ 2185.090597] [<ffffffff810d3bee>] handle_irq_event_percpu+0x3e/0x1a0 Jul 21 10:11:42 dioo-XPS kernel: [ 2185.090599] [<ffffffff810d3d91>] handle_irq_event+0x41/0x70 Jul 21 10:11:42 dioo-XPS kernel: [ 2185.090600] [<ffffffff8...

...nouveau] [ 1079.221906] [<ffffffffa04c6a9e>] ? nvkm_notify_send+0x3e/0x130 [nouveau] [ 1079.221950] [<ffffffffa04c4d28>] ? nvkm_event_send+0xc8/0xe0 [nouveau] [ 1079.222001] [<ffffffffa051627d>] ? nvkm_disp_vblank+0x3d/0x60 [nouveau] [ 1079.222052] [<ffffffffa0504d40>] ? nvkm_mc_intr+0x70/0x110 [nouveau] [ 1079.222100] [<ffffffffa05091d1>] ? nvkm_pci_intr+0x51/0x90 [nouveau] [ 1079.222134] [<ffffffff810c683d>] ? handle_irq_event_percpu+0x6d/0x170 [ 1079.222166] [<ffffffff810c6979>] ? handle_irq_event+0x39/0x60 [ 1079.222195] [<ffffffff810c9a24>] ? ha...

This is an initial series of patches to improve channel recovery on Turing GPUs with the goal of improving reliability enough to eventually enable SVM for Turing. It's likely follow up patches will be required to fully address problems with less trivial workloads than what I have been able to test thus far. This series primarily addresses a number of hardware changes to interrupt layout and

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

We are slowly getting there! v4 of the series with some realy good improvements, so I am sure this is like 95% done and only needs some proper polishing and proper Reviews! I also added the NvVoltOffsetmV module parameter, so that a user is able to over and !under!-volt the GPU. Overvolting makes sense, when there are still some reclocking issues left, which might be solved by a higher voltage.