search for: nvkm_pcie_speed_8_0

overall the same as the old stuff, but with better namings and tirivialy improved code here and there Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement generic code for PCIe speed change pci: implement pcie speed change for tesla pci: implement pcie speed change on Fermi pci: implement PCIe speed change for kepler+ bios/perf: parse the pci speed from the

this patch series implements PCIe speed changes for Tesla and newer. The Kepler and Fermi bits are tested on my cards at home. Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement generic code for PCIe speed change pci: implement pcie speed change for tesla pci: implement pcie speed change on Fermi pci: implement PCIe speed change for kepler+ bios/perf:

overall it is for the most part the same as my older version. I cleaned up some copyright things, so that it is more like the others. Also I moved the print about the max speed supported into preinit and did some other minor cleanups in the 3rd commit. Happy testing (and performance for prime offloading setups) Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement

...(nvbios_rd08(bios, perf + 0xb) & 0x3) { - case 0: - info->pcie_speed = NVKM_PCIE_SPEED_5_0; - break; - case 3: - case 1: + switch (nvbios_rd08(bios, perf + 0xb) & 0x21) { + case 0x01: info->pcie_speed = NVKM_PCIE_SPEED_2_5; break; - case 2: - info->pcie_speed = NVKM_PCIE_SPEED_8_0; + case 0x20: + info->pcie_speed = NVKM_PCIE_SPEED_5_0; break; + case 0x00: default: + info->pcie_speed = NVKM_PCIE_SPEED_8_0; break; } info->pcie_width = 0xff; -- 2.12.2

...bios, perf + 0xb) & 0x3) { - case 0: - info->pcie_speed = NVKM_PCIE_SPEED_5_0; - break; - case 3: - case 1: + switch (nvbios_rd08(bios, perf + 0xb) & 0x21) { + case 0x01: + case 0x21: info->pcie_speed = NVKM_PCIE_SPEED_2_5; break; - case 2: - info->pcie_speed = NVKM_PCIE_SPEED_8_0; + case 0x20: + info->pcie_speed = NVKM_PCIE_SPEED_5_0; break; + case 0x00: default: + info->pcie_speed = NVKM_PCIE_SPEED_8_0; break; } info->pcie_width = 0xff; -- 2.12.2

...device *device = pci->subdev.device; > + if (!device->has_runpm || !suspend) > + return 0; > + > + if (!nvkm_boolopt(device->cfgopt, "NvRunpmWorkaround", true)) > + return 0; > + > + return nvkm_pcie_set_link(pci, NVKM_PCIE_SPEED_8_0, 16, false); > +} > + > void > nvkm_pcie_force_aspm_off(struct nvkm_pci *pci, bool status) > { > @@ -120,7 +136,8 @@ nvkm_pcie_force_aspm_off(struct nvkm_pci *pci, bool status) > } > > int > -nvkm_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8...

this code is pretty usefull for now as nothing triggers it, but the link speed can be changed with a "gk104_pcie_set_link(pci, NVKM_PCIE_SPEED_8_0, 16);" as the last call inside gk104_pcie_init. In the future this should be helpful when using reverse prime with high resolutions on Pascal GPUs. I still need to verify this with a mmiotrace and do more testing, but everybody suffering from bad reverse prime performance or just wanting to...

...vice->has_runpm || !suspend) > > > + return 0; > > > + > > > + if (!nvkm_boolopt(device->cfgopt, "NvRunpmWorkaround", true)) > > > + return 0; > > > + > > > + return nvkm_pcie_set_link(pci, NVKM_PCIE_SPEED_8_0, 16, false); > > > +} > > > + > > > void > > > nvkm_pcie_force_aspm_off(struct nvkm_pci *pci, bool status) > > > { > > > @@ -120,7 +136,8 @@ nvkm_pcie_force_aspm_off(struct nvkm_pci *pci, bool status) > > > } > > > > &gt...

not much changed since the last time I sent those patches out, but there are a couple of annoying bug fixes, which users would probably never hit unless they do rmmod/modprobe nouveau cycles. Biggest change is that I force the link to a 8.0 speed rather than the speed the GPU came up with. Also this series depends on the PCIe improvement patches I sent out recently. Karol Herbst (4): pci:

...} +int +nvkm_pcie_fini(struct nvkm_pci *pci, bool suspend) +{ + struct nvkm_device *device = pci->subdev.device; + if (!device->has_runpm || !suspend) + return 0; + + if (!nvkm_boolopt(device->cfgopt, "NvRunpmWorkaround", true)) + return 0; + + return nvkm_pcie_set_link(pci, NVKM_PCIE_SPEED_8_0, 16, false); +} + void nvkm_pcie_force_aspm_off(struct nvkm_pci *pci, bool status) { @@ -120,7 +136,8 @@ nvkm_pcie_force_aspm_off(struct nvkm_pci *pci, bool status) } int -nvkm_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8 width) +nvkm_pcie_set_link(struct nvkm_pci *pci,...

...ice; > > + if (!device->has_runpm || !suspend) > > + return 0; > > + > > + if (!nvkm_boolopt(device->cfgopt, "NvRunpmWorkaround", true)) > > + return 0; > > + > > + return nvkm_pcie_set_link(pci, NVKM_PCIE_SPEED_8_0, 16, false); > > +} > > + > > void > > nvkm_pcie_force_aspm_off(struct nvkm_pci *pci, bool status) > > { > > @@ -120,7 +136,8 @@ nvkm_pcie_force_aspm_off(struct nvkm_pci *pci, bool status) > > } > > > > int > > -nvkm_pcie_set_link(str...

...) > > > > + return 0; > > > > + > > > > + if (!nvkm_boolopt(device->cfgopt, "NvRunpmWorkaround", true)) > > > > + return 0; > > > > + > > > > + return nvkm_pcie_set_link(pci, NVKM_PCIE_SPEED_8_0, 16, false); > > > > +} > > > > + > > > > void > > > > nvkm_pcie_force_aspm_off(struct nvkm_pci *pci, bool status) > > > > { > > > > @@ -120,7 +136,8 @@ nvkm_pcie_force_aspm_off(struct nvkm_pci *pci, bool status) > > &...

I merged the both series I sent out recently into one bigger one so that it's more obvious on why all of that is needed. Biggest changes since last sent: * reworked the ASPM patch * removed "pci: add nvkm_pcie_get_speed" patch Please test this on Laptops and report back if it either breaks something or doesn't fix runpm. Thanks Karol Herbst (6): pci: disable ASPM before

Changes since last sent: * add a patch to set the device into DRM_SWITCH_POWER_CHANGING state (can be dropped actually, I thought I was needing it, came up with a different approach and forgot to delete it, doesn't hurt though) * expose information about runtime suspending to nvkm so that we can run the pcie workaround only on runtime suspend Karol Herbst (8): pci: disable ASPM