Displaying 5 results from an estimated 5 matches for "nvkm_pcie_speed_5_0".
2015 Oct 13
12
[PATCH v2 0/9] PCIEs speed change
overall the same as the old stuff, but with better namings and tirivialy
improved code here and there
Karol Herbst (9):
pci: add gk104 variant
pci: add gf106 variant
pci: implement generic code for PCIe speed change
pci: implement pcie speed change for tesla
pci: implement pcie speed change on Fermi
pci: implement PCIe speed change for kepler+
bios/perf: parse the pci speed from the
2016 Jan 01
9
[PATCH v4 0/9] PCIe speed changes
overall it is for the most part the same as my older version.
I cleaned up some copyright things, so that it is more like the others.
Also I moved the print about the max speed supported into preinit and did
some other minor cleanups in the 3rd commit.
Happy testing (and performance for prime offloading setups)
Karol Herbst (9):
pci: add gk104 variant
pci: add gf106 variant
pci: implement
2015 Oct 12
12
[PATCH 0/9] PCIe speed changes
this patch series implements PCIe speed changes for Tesla and newer.
The Kepler and Fermi bits are tested on my cards at home.
Karol Herbst (9):
pci: add gk104 variant
pci: add gf106 variant
pci: implement generic code for PCIe speed change
pci: implement pcie speed change for tesla
pci: implement pcie speed change on Fermi
pci: implement PCIe speed change for kepler+
bios/perf:
2017 Apr 05
0
[PATCH] bios/perf: Correctly parse PCIe speeds for ver 0x40
.../subdev/bios/perf.c
+++ b/drm/nouveau/nvkm/subdev/bios/perf.c
@@ -146,18 +146,16 @@ nvbios_perfEp(struct nvkm_bios *bios, int idx,
break;
case 0x40:
info->voltage = nvbios_rd08(bios, perf + 0x02);
- switch (nvbios_rd08(bios, perf + 0xb) & 0x3) {
- case 0:
- info->pcie_speed = NVKM_PCIE_SPEED_5_0;
- break;
- case 3:
- case 1:
+ switch (nvbios_rd08(bios, perf + 0xb) & 0x21) {
+ case 0x01:
info->pcie_speed = NVKM_PCIE_SPEED_2_5;
break;
- case 2:
- info->pcie_speed = NVKM_PCIE_SPEED_8_0;
+ case 0x20:
+ info->pcie_speed = NVKM_PCIE_SPEED_5_0;
break;
+ case...
2017 Apr 06
0
[PATCH v2] bios/perf: Parse PCIe speeds correctly for ver 0x40
.../subdev/bios/perf.c
+++ b/drm/nouveau/nvkm/subdev/bios/perf.c
@@ -146,18 +146,17 @@ nvbios_perfEp(struct nvkm_bios *bios, int idx,
break;
case 0x40:
info->voltage = nvbios_rd08(bios, perf + 0x02);
- switch (nvbios_rd08(bios, perf + 0xb) & 0x3) {
- case 0:
- info->pcie_speed = NVKM_PCIE_SPEED_5_0;
- break;
- case 3:
- case 1:
+ switch (nvbios_rd08(bios, perf + 0xb) & 0x21) {
+ case 0x01:
+ case 0x21:
info->pcie_speed = NVKM_PCIE_SPEED_2_5;
break;
- case 2:
- info->pcie_speed = NVKM_PCIE_SPEED_8_0;
+ case 0x20:
+ info->pcie_speed = NVKM_PCIE_SPEED_5_0;
b...