search for: nvkm_falcon_load_dmem

...{ struct nvkm_device *device = falcon->owner->device; - u32 cmdline_size = NVKM_MSGQUEUE_CMDLINE_SIZE; - u8 buf[cmdline_size]; + u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE]; - memset(buf, 0, cmdline_size); + memset(buf, 0, NVKM_MSGQUEUE_CMDLINE_SIZE); nvkm_msgqueue_write_cmdline(queue, buf); - nvkm_falcon_load_dmem(falcon, buf, addr_args, cmdline_size, 0); + nvkm_falcon_load_dmem(falcon, buf, addr_args, + NVKM_MSGQUEUE_CMDLINE_SIZE, 0); /* rearm the queue so it will wait for the init message */ nvkm_msgqueue_reinit(queue); -- 2.7.4

...; - u32 cmdline_size = NVKM_MSGQUEUE_CMDLINE_SIZE; >> - u8 buf[cmdline_size]; >> + u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE]; >> >> - memset(buf, 0, cmdline_size); >> + memset(buf, 0, NVKM_MSGQUEUE_CMDLINE_SIZE); >> nvkm_msgqueue_write_cmdline(queue, buf); >> - nvkm_falcon_load_dmem(falcon, buf, addr_args, cmdline_size, 0); >> + nvkm_falcon_load_dmem(falcon, buf, addr_args, >> + NVKM_MSGQUEUE_CMDLINE_SIZE, 0); > > I think I'd use 'sizeof (buf)' in both those lines. > Yeah. I like it. I'll send v2 with that change shortly. Thank...

...on->owner->device; > - u32 cmdline_size = NVKM_MSGQUEUE_CMDLINE_SIZE; > - u8 buf[cmdline_size]; > + u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE]; > > - memset(buf, 0, cmdline_size); > + memset(buf, 0, NVKM_MSGQUEUE_CMDLINE_SIZE); > nvkm_msgqueue_write_cmdline(queue, buf); > - nvkm_falcon_load_dmem(falcon, buf, addr_args, cmdline_size, 0); > + nvkm_falcon_load_dmem(falcon, buf, addr_args, > + NVKM_MSGQUEUE_CMDLINE_SIZE, 0); I think I'd use 'sizeof (buf)' in both those lines. David

...quick check can you try changing > > > > > > > > drivers/gpu/drm/nouveau/nvkm/core/firmware.c:nvkm_firmware_mem_target > > > > from NVKM_MEM_TARGET_HOST to NVKM_MEM_TARGET_NCOH ? > > > In addition to Dave's change, can you try changing the > > nvkm_falcon_load_dmem() call in gm20b_pmu_init() to: > > > > nvkm_falcon_pio_wr(falcon, (u8 *)&args, 0, 0, DMEM, addr_args, > > sizeof(args), 0, false); > > Hello! > > Chiming in just to say that with this change I see the same as Nicolas > except that the init message size is 255 in...

...gt; > > > > > > drivers/gpu/drm/nouveau/nvkm/core/firmware.c:nvkm_firmware_mem_target > > > > > > from NVKM_MEM_TARGET_HOST to NVKM_MEM_TARGET_NCOH ? > > > > > > > In addition to Dave's change, can you try changing the > > > > nvkm_falcon_load_dmem() call in gm20b_pmu_init() to: > > > > > > > > nvkm_falcon_pio_wr(falcon, (u8 *)&args, 0, 0, DMEM, addr_args, > > > > sizeof(args), 0, false); > > > > > > Chiming in just to say that with this change I see the same as Nicolas > > >...

...u32 addr_args) { struct nvkm_device *device = falcon->owner->device; - u32 cmdline_size = NVKM_MSGQUEUE_CMDLINE_SIZE; - u8 buf[cmdline_size]; + u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE]; - memset(buf, 0, cmdline_size); + memset(buf, 0, sizeof(buf)); nvkm_msgqueue_write_cmdline(queue, buf); - nvkm_falcon_load_dmem(falcon, buf, addr_args, cmdline_size, 0); + nvkm_falcon_load_dmem(falcon, buf, addr_args, sizeof(buf), 0); /* rearm the queue so it will wait for the init message */ nvkm_msgqueue_reinit(queue); -- 2.7.4

...con *falcon, code_size, hsbl_desc->start_tag, 0, false); /* Generate the BL header */ - memset(bl_desc, 0, bl_desc_size); acr->func->generate_hs_bl_desc(load_hdr, bl_desc, offset); /* @@ -811,6 +829,7 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon, nvkm_falcon_load_dmem(falcon, bl_desc, hsbl_desc->dmem_load_off, bl_desc_size, 0); + kfree(bl_desc); return hsbl_desc->start_tag << 8; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c index 866877b88797..978ad07903...

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

...e); > > /* Generate the BL header */ > - memset(bl_desc, 0, bl_desc_size); > acr->func->generate_hs_bl_desc(load_hdr, bl_desc, offset); > > /* > @@ -811,6 +829,7 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon, > nvkm_falcon_load_dmem(falcon, bl_desc, hsbl_desc->dmem_load_off, > bl_desc_size, 0); > > + kfree(bl_desc); > return hsbl_desc->start_tag << 8; > } > > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c b/drivers/gpu/drm/nouvea...

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

...falcon_mask(struct nvkm_falcon *falcon, u32 addr, u32 mask, u32 val) +{ + struct nvkm_device *device = falcon->subdev->device; + + return nvkm_mask(device, falcon->addr + addr, mask, val); +} + +void nvkm_falcon_load_imem(struct nvkm_falcon *, void *, u32, u32, u16, u8, + bool); +void nvkm_falcon_load_dmem(struct nvkm_falcon *, void *, u32, u32, u8); +void nvkm_falcon_read_dmem(struct nvkm_falcon *, u32, u32, u8, void *); +void nvkm_falcon_bind_context(struct nvkm_falcon *, struct nvkm_gpuobj *); +void nvkm_falcon_set_start_addr(struct nvkm_falcon *, u32); +void nvkm_falcon_start(struct nvkm_falcon *...

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot: