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...and voltage devices optional, and allowing pstates to be provided >> directly instead of being probed using the BIOS (which Tegra does not have). >> >> The last patch adds the GK20A clock device. Arguably the clock can be seen as a >> stripped-down version of what is seen on NVE0, however instead of using NVE0 >> support has been written from scratch using the ChromeOS kernel as a basis. >> There are several reasons for this: >> >> - The ChromeOS driver uses a lookup table for the P coefficient which I could >> not find in the NVE0 driver, &...

On Sat, Feb 01, 2014 at 12:16:54PM +0900, Alexandre Courbot wrote: > GK20A's FIFO is compatible with NVE0, but only features 128 channels and > 1 runlist. > > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> > --- > drivers/gpu/drm/nouveau/Makefile | 1 + > drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h | 1 + > drivers/gpu/drm/nouveau/core/...

...was not correct. This is inconsequential for GK20A which only features one runlist, but other GPUs might run into troubles because of this. Not tested, just reported for your consideration. FWIW, the Android GK20A driver uses the same offset calculation. drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c index 99c9dee..dbc3ff6 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/...

Signed-off-by: John Rowley <john.rowley08 at gmail.com> --- nvkm/engine/device/nve0.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/nvkm/engine/device/nve0.c b/nvkm/engine/device/nve0.c index 964c183..6e72f9c 100644 --- a/nvkm/engine/device/nve0.c +++ b/nvkm/engine/device/nve0.c @@ -208,6 +208,41 @@ nve0_identify(struct nouveau_device *de...

On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot <acourbot at nvidia.com> wrote: > Set the correct subdev/engine classes when GK20A (0xea) is probed. > > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> > --- > drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c > index 987edbc30a09..8509dd57de1f 100644 > --- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c &...

...nd object class definitions ab60619 drm/nouveau/instmem: tidy up the object class definition 24a4ae8 drm/nouveau/instmem: tidy up the subdev class definition 64c672a drm/nouveau/pwr: implement a simple i2c stack 2e9dfe2 drm/nouveau/pwr: have rd/wr32 routines clobber data instead of addr 7321623 drm/nve0/fb: turn off some bits in 10f584 at init cb54dd2 drm/nve0/fb/gddr5: merge a fix from ddr3 for one of the timing settings b13d0e4 drm/nve0/fb/gddr5: yet another random 10f200 bit c814a60 drm/nvc0-/fb: hook up skeleton interrupt handler 7f39e59 drm/nve0/fb/gddr5: more 10f200 stuff 12642e3 drm/nve0/cl...

....) The impact to the code is pretty minor. Depending on the situation it's easier to either ifdef out code or to provide stubs for functions. What do people think about this? It shouldn't be too difficult for me to extend this to categories like <pre-nv50> <nv50-nvc0> <nvc0-nve0> <nve0+>, or maybe even more fine-grained, esp since nvd0 is when a lot of changes happened. Or maybe less-fine-grained and keep the nvc0/nve0 cards under one option. Feedback appreciated. Not-Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drivers/gpu/drm/nouveau/Kconf...

LTC device is now required for PGRAPH to work, add it. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- nvkm/engine/device/nve0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/nvkm/engine/device/nve0.c b/nvkm/engine/device/nve0.c index 54ec53bc6252..cdf9147f32a1 100644 --- a/nvkm/engine/device/nve0.c +++ b/nvkm/engine/device/nve0.c @@ -163,6 +163,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[N...

...he code is pretty minor. Depending on the situation it's easier > to either ifdef out code or to provide stubs for functions. > > What do people think about this? It shouldn't be too difficult for me to > extend this to categories like <pre-nv50> <nv50-nvc0> <nvc0-nve0> <nve0+>, or > maybe even more fine-grained, esp since nvd0 is when a lot of changes > happened. Or maybe less-fine-grained and keep the nvc0/nve0 cards under one > option. > > Feedback appreciated. > > Not-Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> &gt...

GK20A's FIFO is compatible with NVE0, but only features 128 channels and 1 runlist. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h | 1 + drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c | 27 ++++++++...

Memory was always allocated for 4096 channels. Change this to allocate what we actually need according to the number of channels we use. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c index 9a850fe19515..99c9deea248f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/cor...

GK20A's FIFO is compatible with NVE0, but only features 128 channels and 1 runlist. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h | 1 + drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c | 35 ++++++++...

...making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down version of what is seen on NVE0, however instead of using NVE0 support has been written from scratch using the ChromeOS kernel as a basis. There are several reasons for this: - The ChromeOS driver uses a lookup table for the P coefficient which I could not find in the NVE0 driver, - Some registers that NVE0 expects to find are...

...he > thermal and voltage devices optional, and allowing pstates to be provided > directly instead of being probed using the BIOS (which Tegra does not have). > > The last patch adds the GK20A clock device. Arguably the clock can be seen as a > stripped-down version of what is seen on NVE0, however instead of using NVE0 > support has been written from scratch using the ChromeOS kernel as a basis. > There are several reasons for this: > > - The ChromeOS driver uses a lookup table for the P coefficient which I could > not find in the NVE0 driver, > - Some registers...

...L246WH screen with 1600x1200 (native) and 800x600 resolutions with scaling disabled on all 3 HDMI-capable outputs (HDMI-1, DVI-D-1, DVI-D-2) available. Audio output was tested on HDMI-1 output. --- drivers/gpu/drm/nouveau/Makefile | 1 + .../gpu/drm/nouveau/core/engine/disp/hdminve0.c | 91 ++++++++++++++++++++++ drivers/gpu/drm/nouveau/core/engine/disp/nv50.h | 1 + drivers/gpu/drm/nouveau/core/engine/disp/nve0.c | 2 +- 4 files changed, 94 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c diff --git a/drivers/gpu...

https://bugs.freedesktop.org/show_bug.cgi?id=105432 Bug ID: 105432 Summary: [NVE0] Display Freezes but SSH Works When Using OpenGL Applications Product: xorg Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: major Priority: medium Compone...

...manage to before the next merge window either. So, I'll likely take these patches as-is (assuming no objections on reviews here) and rebase my stuff on top. > > The last patch adds the GK20A clock device. Arguably the clock can be seen as a > stripped-down version of what is seen on NVE0, however instead of using NVE0 > support has been written from scratch using the ChromeOS kernel as a basis. > There are several reasons for this: > > - The ChromeOS driver uses a lookup table for the P coefficient which I could > not find in the NVE0 driver, Interesting. Can you...

...rmware that's on the card (or with dedicated hardware, who knows) so all that's left is providing the little "os" running on the connected falcon processors. Unless you're booting with nouveau.NvGrUseFW=1, you don't need the pgraph firmware. It generally tends to work for nve0 cards nowadays, although some people have issues with hangs (e.g. https://bugs.freedesktop.org/show_bug.cgi?id=70354, https://bugs.freedesktop.org/show_bug.cgi?id=72180). I believe there were a bunch of fixes to the fuc ucode in 3.11, which is probably why Martin suggested you use a more recent ker...

...ceh at nvidia.com> wrote: > This is a workaround to avoid the instmem backup/restore during the suspend > and resume process in nv50 instemem driver. > > Signed-off-by: Vince Hsu <vinceh at nvidia.com> > --- > drm/Kbuild | 1 + > nvkm/engine/device/nve0.c | 2 +- > nvkm/include/subdev/instmem.h | 1 + > nvkm/subdev/instmem/gk20a.c | 70 +++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 73 insertions(+), 1 deletion(-) > create mode 100644 nvkm/subdev/instmem/gk20a.c > > diff --git a/drm/Kbuild b/drm/Kbuild &g...

...ve). Oh and while I'm at it, there seems to be a typo in line 131 of clock.h, which should read _nouveau_clock_fini and not _nouveau_clock_init. >> >> The last patch adds the GK20A clock device. Arguably the clock can be seen as a >> stripped-down version of what is seen on NVE0, however instead of using NVE0 >> support has been written from scratch using the ChromeOS kernel as a basis. >> There are several reasons for this: >> >> - The ChromeOS driver uses a lookup table for the P coefficient which I could >> not find in the NVE0 driver, &...