Displaying 16 results from an estimated 16 matches for "nvc0_xv".
2018 Feb 04
0
[PATCH 2/2] nv50/xv: add support for depth 30 xv output
Ostensibly it should probably be looking at the pixmap format. However
it's always the window pixmap, so we can assume it's what we expect.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nouveau_xv.c | 11 +++++++++--
src/nv50_xv.c | 3 ++-
src/nvc0_xv.c | 3 ++-
3 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/src/nouveau_xv.c b/src/nouveau_xv.c
index 0b6c4d4..2f1979a 100644
--- a/src/nouveau_xv.c
+++ b/src/nouveau_xv.c
@@ -112,6 +112,13 @@ XF86VideoFormatRec NVFormats[NUM_FORMATS_ALL] =
{15, DirectColor}, {16, DirectColor},...
2016 Oct 17
2
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...However GM20x and GP10x also use this TIC format.
>
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
> ---
> src/nvc0_accel.c | 11 ++++++++++
> src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
> src/nvc0_exa.c | 22 ++++---------------
> src/nvc0_xv.c | 67 +++++++++++++++++++-------------------------------------
> 4 files changed, 93 insertions(+), 63 deletions(-)
>
> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
> index 0682806..8da5051 100644
> --- a/src/nvc0_accel.c
> +++ b/src/nvc0_accel.c
> @@ -322,6 +322,17 @@...
2018 Feb 04
1
[PATCH 1/2] dri3: remove bogus condition for creating pixmap
Not clear what the depth % 8 was trying to protect against, but it was
breaking 30bpp visuals with DRI3. Add it in to ensure that bitsPerPixel
% 8 is 0, since there is plenty of bpp/8 math in the driver.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nouveau_dri2.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/nouveau_dri2.c b/src/nouveau_dri2.c
2012 Jul 27
1
[PATCH] nvc0: Add and enable vblank support
...+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "No kernel support for GLX sync to VBlank.\n");
+ pNv->glx_vblank = false;
+ }
+
BEGIN_NVC0(push, NV01_SUBC(3D, OBJECT), 1);
PUSH_DATA (push, pNv->Nv3D->handle);
BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
index 3b6d01f..86b7948 100644
--- a/src/nvc0_xv.c
+++ b/src/nvc0_xv.c
@@ -221,9 +221,8 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
PUSH_DATAf(push, 1.0 / width);
PUSH_DATAf(push, 1.0 / height);
- if (0 && pPriv->SyncToVBlank) {
- NV50SyncToVBlank(ppix, dstBox);
- }
+...
2015 Mar 14
1
[PATCH ddx] Add support for VRAM-less devices to the ddx
...| NOUVEAU_BO_WR);
if (pmpict && pmpict->pDrawable)
PUSH_REFN (push, nouveau_pixmap_bo(pmpix),
- NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+ NOUVEAU_BO_APER | NOUVEAU_BO_RD);
nouveau_pushbuf_bufctx(push, pNv->bufctx);
if (nouveau_pushbuf_validate(push)) {
diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
index d1d8f18..31e2309 100644
--- a/src/nvc0_xv.c
+++ b/src/nvc0_xv.c
@@ -69,9 +69,9 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
NVPtr pNv = NVPTR(pScrn);
struct nouveau_bo *dst = nouveau_pixmap_bo(ppix);
struct nouveau_pushbuf_refn refs[] = {
- { pNv->scratch, NOUVEAU_BO_VR...
2016 Oct 16
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...mat, which is what I tested
with. However GM20x and GP10x also use this TIC format.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nvc0_accel.c | 11 ++++++++++
src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
src/nvc0_exa.c | 22 ++++---------------
src/nvc0_xv.c | 67 +++++++++++++++++++-------------------------------------
4 files changed, 93 insertions(+), 63 deletions(-)
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 0682806..8da5051 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pS...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...mat, which is what I tested
with. However GM20x and GP10x also use this TIC format.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nvc0_accel.c | 11 ++++++++++
src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
src/nvc0_exa.c | 23 ++++---------------
src/nvc0_xv.c | 67 +++++++++++++++++++-------------------------------------
4 files changed, 93 insertions(+), 64 deletions(-)
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 0682806..8da5051 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pS...
2016 Oct 17
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...use this TIC format.
>>
>> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
>> ---
>> src/nvc0_accel.c | 11 ++++++++++
>> src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
>> src/nvc0_exa.c | 22 ++++---------------
>> src/nvc0_xv.c | 67
>> +++++++++++++++++++-------------------------------------
>> 4 files changed, 93 insertions(+), 63 deletions(-)
>>
>> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
>> index 0682806..8da5051 100644
>> --- a/src/nvc0_accel.c
>> +++ b/src/nvc0_...
2016 Oct 27
2
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...However GM20x and GP10x also use this TIC format.
>
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
> ---
> src/nvc0_accel.c | 11 ++++++++++
> src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
> src/nvc0_exa.c | 23 ++++---------------
> src/nvc0_xv.c | 67 +++++++++++++++++++-------------------------------------
> 4 files changed, 93 insertions(+), 64 deletions(-)
>
> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
> index 0682806..8da5051 100644
> --- a/src/nvc0_accel.c
> +++ b/src/nvc0_accel.c
> @@ -322,6 +322,17 @@...
2012 Apr 11
1
[error] xf86-video-nouveau on OpenBSD
...t;/usr/X11R6/share/aclocal" >> /usr/local/share/aclocal/dirlist
./configure --enable-nouveau-experimental-api
make
make install
There wasn't any problem.
Then, I try to compile xf86-video-nouveau with :
./configure
make
But I get this error message :
CC nvc0_exa.lo
CC nvc0_xv.lo
CC drmmode_display.lo
drmmode_display.c: In function 'drmmode_page_flip':
drmmode_display.c:1319: warning: implicit declaration of function
'drmModePageFlip'
drmmode_display.c: In function 'drmmode_screen_init':
drmmode_display.c:1476: error: 'drmEventContext...
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
...2 +-
src/nouveau_local.h | 2 +-
src/nouveau_xv.c | 2 +-
src/nv_accel_common.c | 1 +
src/nv_driver.c | 3 +
src/nvc0_accel.c | 68 +++-
src/nvc0_accel.h | 57 +++
src/nvc0_exa.c | 71 ++--
src/nvc0_xv.c | 115 +++---
src/shader/Makefile | 23 +-
src/shader/exac8nv110.fp | 47 +++
src/shader/exac8nv110.fpc | 38 ++
src/shader/exacanv110.fp | 47 +++
src/shader/exacanv110.fpc | 38 ++
src/shader/exacmnv110.fp | 47 +++
src/shader/exacmn...
2016 Oct 16
2
[PATCH] exa: add GM10x acceleration support
...6 ++++++++
src/nouveau_copy.c | 1 +
src/nouveau_exa.c | 2 +-
src/nouveau_xv.c | 2 +-
src/nv_accel_common.c | 1 +
src/nv_driver.c | 1 +
src/nvc0_accel.c | 37 ++++++++++++++---
src/nvc0_exa.c | 48 ++++++++++++++++++++--
src/nvc0_xv.c | 48 ++++++++++++++++++++--
src/shader/Makefile | 23 ++++++++---
src/shader/exac8nv110.fp | 47 +++++++++++++++++++++
src/shader/exac8nv110.fpc | 38 +++++++++++++++++
src/shader/exacanv110.fp | 47 +++++++++++++++++++++
src/shader/exacanv110.fpc | 38 +++++++++++++++++...
2016 Oct 27
0
[PATCH v2 1/7] exa: add GM10x acceleration support
...6 ++++++++
src/nouveau_copy.c | 1 +
src/nouveau_exa.c | 2 +-
src/nouveau_xv.c | 2 +-
src/nv_accel_common.c | 1 +
src/nv_driver.c | 1 +
src/nvc0_accel.c | 37 ++++++++++++++---
src/nvc0_exa.c | 48 ++++++++++++++++++++--
src/nvc0_xv.c | 48 ++++++++++++++++++++--
src/shader/Makefile | 23 ++++++++---
src/shader/exac8nv110.fp | 47 +++++++++++++++++++++
src/shader/exac8nv110.fpc | 38 +++++++++++++++++
src/shader/exacanv110.fp | 47 +++++++++++++++++++++
src/shader/exacanv110.fpc | 38 +++++++++++++++++...
2016 Oct 17
0
[PATCH] exa: add GM10x acceleration support
...| 1 +
> src/nouveau_exa.c | 2 +-
> src/nouveau_xv.c | 2 +-
> src/nv_accel_common.c | 1 +
> src/nv_driver.c | 1 +
> src/nvc0_accel.c | 37 ++++++++++++++---
> src/nvc0_exa.c | 48 ++++++++++++++++++++--
> src/nvc0_xv.c | 48 ++++++++++++++++++++--
> src/shader/Makefile | 23 ++++++++---
> src/shader/exac8nv110.fp | 47 +++++++++++++++++++++
> src/shader/exac8nv110.fpc | 38 +++++++++++++++++
> src/shader/exacanv110.fp | 47 +++++++++++++++++++++
> src/shader/exacanv110.fp...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...use this TIC format.
>>
>> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
>> ---
>> src/nvc0_accel.c | 11 ++++++++++
>> src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
>> src/nvc0_exa.c | 23 ++++---------------
>> src/nvc0_xv.c | 67
>> +++++++++++++++++++-------------------------------------
>> 4 files changed, 93 insertions(+), 64 deletions(-)
>>
>> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
>> index 0682806..8da5051 100644
>> --- a/src/nvc0_accel.c
>> +++ b/src/nvc0_...
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
These are copied directly from the mesa repository.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++
src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++----------------
2 files changed, 892 insertions(+), 340 deletions(-)
create mode 100644 src/hwdefs/gm107_texture.xml.h
diff --git