Displaying 7 results from an estimated 7 matches for "nvc0_bar_dtor".
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nvc0_bar_ctor
2014 Jun 27
5
[PATCH 1/2] drm/nouveau/bar: add noncached ioremap property
Some BARs (like GK20A's) do not support being ioremapped write-combined.
Add a boolean property to the BAR structure and handle that case in the
Nouveau BO implementation.
Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
---
drivers/gpu/drm/nouveau/core/include/subdev/bar.h | 3 +++
drivers/gpu/drm/nouveau/nouveau_bo.c | 17 ++++++++++++-----
2 files changed, 15
2014 Jun 28
1
[PATCH v2] drm/gk20a: add BAR instance
...n 0;
>>>+}
>>>+
>>>+struct nouveau_oclass
>>>+gk20a_bar_oclass = {
>>>+ .handle = NV_SUBDEV(BAR, 0xea),
>>>+ .ofuncs = &(struct nouveau_ofuncs) {
>>>+ .ctor = gk20a_bar_ctor,
>>>+ .dtor = nvc0_bar_dtor,
>>>+ .init = nvc0_bar_init,
>>>+ .fini = _nouveau_bar_fini,
>>>+ },
>>>+};
>>>diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
>>>b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
>>>index ca813...
2014 Jun 27
0
[PATCH 2/2] drm/gk20a: add BAR instance
...nt, engine, oclass, data, size, pobject);
+ if (ret)
+ return ret;
+
+ bar = *pobject;
+ bar->iomap_uncached = true;
+
+ return 0;
+}
+
+struct nouveau_oclass
+gk20a_bar_oclass = {
+ .handle = NV_SUBDEV(BAR, 0xea),
+ .ofuncs = &(struct nouveau_ofuncs) {
+ .ctor = gk20a_bar_ctor,
+ .dtor = nvc0_bar_dtor,
+ .init = nvc0_bar_init,
+ .fini = _nouveau_bar_fini,
+ },
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
index ca8139b9ab27..0a44459844e3 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
+++ b/drivers/gpu/drm/nouveau/c...
2014 Jun 28
0
[PATCH v2] drm/gk20a: add BAR instance
...;
>>+
>>+ return 0;
>>+}
>>+
>>+struct nouveau_oclass
>>+gk20a_bar_oclass = {
>>+ .handle = NV_SUBDEV(BAR, 0xea),
>>+ .ofuncs = &(struct nouveau_ofuncs) {
>>+ .ctor = gk20a_bar_ctor,
>>+ .dtor = nvc0_bar_dtor,
>>+ .init = nvc0_bar_init,
>>+ .fini = _nouveau_bar_fini,
>>+ },
>>+};
>>diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
>>b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
>>index ca8139b9ab27..0a44459844e3 100644...
2014 Feb 04
1
[RFC 07/16] drm/nouveau/bar/nvc0: support chips without BAR3
..., 1) - 1));
> -
> - priv->base.alloc = nouveau_bar_alloc;
> - priv->base.kmap = nvc0_bar_kmap;
> priv->base.umap = nvc0_bar_umap;
> priv->base.unmap = nvc0_bar_unmap;
> priv->base.flush = nv84_bar_flush;
> @@ -176,12 +177,16 @@ nvc0_bar_dtor(struct nouveau_object *object)
> nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd);
> nouveau_gpuobj_ref(NULL, &priv->bar[1].mem);
>
> - if (priv->bar[0].vm) {
> - nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
>...
2014 Feb 01
0
[RFC 07/16] drm/nouveau/bar/nvc0: support chips without BAR3
...nv_wo32(mem, 0x020c, upper_32_bits(nv_device_resource_len(device, 1) - 1));
-
- priv->base.alloc = nouveau_bar_alloc;
- priv->base.kmap = nvc0_bar_kmap;
priv->base.umap = nvc0_bar_umap;
priv->base.unmap = nvc0_bar_unmap;
priv->base.flush = nv84_bar_flush;
@@ -176,12 +177,16 @@ nvc0_bar_dtor(struct nouveau_object *object)
nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd);
nouveau_gpuobj_ref(NULL, &priv->bar[1].mem);
- if (priv->bar[0].vm) {
- nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
- nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->...
2014 Feb 01
28
[RFC 00/16] drm/nouveau: initial support for GK20A (Tegra K1)
Hello everyone,
GK20A is the Kepler-based GPU used in the upcoming Tegra K1 chips. The following
patches perform architectural changes to Nouveau that are necessary to support
non-PCI GPUs and add initial support for GK20A. Although the support is still
very basic and more user-space changes will be needed to make the full graphics
stack run on top of it, we were able to successfully open