search for: nv_ro32

...,25 @@ nvbios_vmap_entry_parse(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len, u16 vmap = nvbios_vmap_entry(bios, idx, ver, len); memset(info, 0x00, sizeof(*info)); switch (!!vmap * *ver) { - case 0x10: + case 0x10: { + s32 accum, b, c; + info->link = 0xff; info->min = nv_ro32(bios, vmap + 0x00); info->max = nv_ro32(bios, vmap + 0x04); - info->arg[0] = nv_ro32(bios, vmap + 0x08); - info->arg[1] = nv_ro32(bios, vmap + 0x0c); - info->arg[2] = nv_ro32(bios, vmap + 0x10); + + accum = nv_ro32(bios, vmap + 0x08); + b = nv_ro32(bios, vmap + 0x0c); + c =...

...uct nv31_mpeg_priv *priv, u32 mthd, u32 arg) { - struct nouveau_instmem *imem = nouveau_instmem(object); - struct nv31_mpeg_priv *priv = (void *)object->engine; - u32 inst = *(u32 *)arg << 4; + struct nouveau_instmem *imem = nouveau_instmem(priv); + u32 inst = arg << 4; u32 dma0 = nv_ro32(imem, inst + 0); u32 dma1 = nv_ro32(imem, inst + 4); u32 dma2 = nv_ro32(imem, inst + 8); @@ -106,13 +105,16 @@ nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len) nv_mask(priv, 0x00b300, 0x000c0000, mem_target << 2); nv_wr32(priv, 0x00b360, base); nv_...

These chipsets include the VP2 engine which is composed of a bitstream processor (BSP) that decodes H.264 and a video processor (VP) which can do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are driven by separate xtensa chips embedded in the hardware. This patch provides the mechanism to load the kernel for the xtensa chips and provide the necessary interactions to do the rest of

...b2..c4e1f08 100644 --- a/drm/nouveau/nvkm/subdev/bios/i2c.c +++ b/drm/nouveau/nvkm/subdev/bios/i2c.c @@ -74,7 +74,11 @@ dcb_i2c_parse(struct nvkm_bios *bios, u8 idx, struct dcb_i2c_entry *info) u16 ent = dcb_i2c_entry(bios, idx, &ver, &len); if (ent) { if (ver >= 0x41) { - if (!(nv_ro32(bios, ent) & 0x80000000)) + u32 ent_value = nv_ro32(bios, ent); + u8 i2c_port = (ent_value >> 27) & 0x1f; + u8 dpaux_port = (ent_value >> 22) & 0x1f; + /* value 0x1f means unused according to DCB 4.x spec */ + if (i2c_port == 0x1f && dpaux_port == 0x1f)...

...ne, oclass, NULL, + 0x10000, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, &engctx); + *pobject = nv_object(engctx); + return ret; +} + +void +_nouveau_xtensa_intr(struct nouveau_subdev *subdev) +{ + struct nouveau_xtensa *xtensa = (void *)subdev; + u32 intr, unk104, unk10c, chan; + + unk104 = nv_ro32(xtensa, 0xd04); + intr = nv_ro32(xtensa, 0xc20); + chan = nv_ro32(xtensa, 0xc28); + unk10c = nv_ro32(xtensa, 0xd0c); + if (intr & 0x10) + nv_warn(xtensa, "Watchdog interrupt, engine hung.\n"); + nv_wo32(xtensa, 0xc20, intr); + intr = nv_ro32(xtensa, 0xc20); + if (unk104 == 0x10001 &a...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drivers/gpu/drm/nouveau/nouveau_connector.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h index 6e399aa..4cefce3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.h +++ b/drivers/gpu/drm/nouveau/nouveau_connector.h @@ -107,7 +107,4

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...ouveau/core/subdev/bios/init.c b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c index de201ba..126651b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c @@ -845,9 +845,8 @@ init_idx_addr_latched(struct nvbios_init *init) u32 data = nv_ro32(bios, init->offset + 13); u8 count = nv_ro08(bios, init->offset + 17); - trace("INDEX_ADDRESS_LATCHED\t" - "R[0x%06x] : R[0x%06x]\n\tCTRL &= 0x%08x |= 0x%08x\n", - creg, dreg, mask, data); + trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n&quo...

...ubdev/therm/nv84.c index 38b16d9..14e2e09 100644 --- a/nvkm/subdev/therm/nv84.c +++ b/nvkm/subdev/therm/nv84.c @@ -33,7 +33,12 @@ struct nv84_therm_priv { int nv84_temp_get(struct nouveau_therm *therm) { - return nv_rd32(therm, 0x20400); + struct nouveau_fuse *fuse = nouveau_fuse(therm); + + if (nv_ro32(fuse, 0x1a8) == 1) + return nv_rd32(therm, 0x20400); + else + return -ENODEV; } void -- 2.0.0

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c index c190043..5c54aa1 100644 --- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c +++

...e 2: + /* TODO: Understand the difference between the two! */ + fan->type = NVBIOS_THERM_FAN_PWM; + break; + default: + fan->type = NVBIOS_THERM_FAN_UNK; + } + + fan->min_duty = nv_ro08(bios, data + 0x02); + fan->max_duty = nv_ro08(bios, data + 0x03); + + fan->pwm_freq = nv_ro32(bios, data + 0x0b) & 0xffffff; + } + return data; +} -- 2.0.0

We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. Signed-off-by: Martin Peres <martin.peres at free.fr> --- configure.ac | 1 + drm/Kbuild | 4 ++ drm/core/include/subdev/fuse.h | 1 + drm/core/subdev/fuse/base.c | 1 + drm/core/subdev/fuse/g80.c | 1 +

Following a series of patches that implement memory reclocking for NVA3/5/8 with DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics cards, but I expect reclocking now to work on many more. Testers can pick up these patches and test it by enabling pstate (nouveau.pstate=1). They should then be able to change clocks by writing to /sys/class/drm/card0/device/pstate. Correct

...char part_str[40]; > + u32 data1; > + char *log_data = kmalloc(GK20A_PMU_TRACE_BUFSIZE, GFP_KERNEL); > + char *trace = log_data; > + u32 *trace1 = (u32 *)log_data; > + for (i = 0; i < GK20A_PMU_TRACE_BUFSIZE; i += 4) { > + data1 = nv_ro32(pmu->trace_buf.pmubufobj, 0x0000 + i); > + memcpy(log_data + i, (void *)(&data1), 32); > + } > + for (i = 0; i < GK20A_PMU_TRACE_BUFSIZE; i += 0x40) { > + for (j = 0; j < 0x40; j++) > + if (trace1[(i / 4) + j]...

...struct pmu_desc *pmu = &impl->pmudata; + u32 i = 0, j = 0, k, l, m; + char part_str[40]; + u32 data1; + char *log_data = kmalloc(GK20A_PMU_TRACE_BUFSIZE, GFP_KERNEL); + char *trace = log_data; + u32 *trace1 = (u32 *)log_data; + for (i = 0; i < GK20A_PMU_TRACE_BUFSIZE; i += 4) { + data1 = nv_ro32(pmu->trace_buf.pmubufobj, 0x0000 + i); + memcpy(log_data + i, (void *)(&data1), 32); + } + for (i = 0; i < GK20A_PMU_TRACE_BUFSIZE; i += 0x40) { + for (j = 0; j < 0x40; j++) + if (trace1[(i / 4) + j]) + break; + if (j == 0x40) + goto out; + seq_printf(s, "Index %x: &quo...

...evo, 0, 0x0084, 1); 149 OUT_RING (evo, 0x00000000); 150 151 nv_wo32(disp->ntfy, 0x000, 0x00000000); 152 FIRE_RING (evo); 153 154 start = ptimer->read(dev); 155 do { 156 if (nv_ro32(disp->ntfy, 0x000)) 157 return 0; 158 } while (ptimer->read(dev) - start < 2000000000ULL); 159 } Looking at hwdocs in envytools documents I found out that 0x0084 is sending FLUSH_CRTL to the card and 0x0080 is sending FLUSH. I...

...char part_str[40]; > + u32 data1; > + char *log_data = kmalloc(GK20A_PMU_TRACE_BUFSIZE, GFP_KERNEL); > + char *trace = log_data; > + u32 *trace1 = (u32 *)log_data; > + for (i = 0; i < GK20A_PMU_TRACE_BUFSIZE; i += 4) { > + data1 = nv_ro32(pmu->trace_buf.pmubufobj, 0x0000 + i); > + memcpy(log_data + i, (void *)(&data1), 32); > + } > + for (i = 0; i < GK20A_PMU_TRACE_BUFSIZE; i += 0x40) { > + for (j = 0; j < 0x40; j++) > + if (trace1[(i / 4) + j]...

...e 2: + /* TODO: Understand the difference between the two! */ + fan->type = NVBIOS_THERM_FAN_PWM; + break; + default: + fan->type = NVBIOS_THERM_FAN_UNK; + } + + fan->min_duty = nv_ro08(bios, data + 0x02); + fan->max_duty = nv_ro08(bios, data + 0x03); + + fan->pwm_freq = nv_ro32(bios, data + 0x0b) & 0xffffff; + } + return data; +} -- 2.0.0

Hi all, First thing first: It works, I now no longer have a few dropped frames every 10s on my testbox here with the pageflip i-g-t tests. Random notes: - New design has per-crtc locks to protect the crtc input-side (pageflip, cursor) for r/w and the output state of the crtc (mode, dpms) as read-only. It also required completely revamped fb lifecycle management, those are now refcounted