search for: nv_mem_access_rw

...ngine/graph/ctxnve4.c index e2de73e..fc1cc32 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c @@ -813,7 +813,7 @@ nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); - mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); + mmio_data(priv->tpc_total << 17, 0x1000, NV_MEM_ACCESS_RW); mmio_list(0x40800c, 0x00000000, 8, 1); mmio_list(0x408010, 0x80000000, 0, 0); mm...

...ngine/graph/ctxnve4.c index e2de73e..ff0960f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c @@ -813,7 +813,7 @@ nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); - mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); + mmio_data(priv->gpc_nr << 17, 0x1000, NV_MEM_ACCESS_RW); mmio_list(0x40800c, 0x00000000, 8, 1); mmio_list(0x408010, 0x80000000, 0, 0); mmio_...

...eau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -252,8 +252,8 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man, node->page_shift = 12; - ret = nouveau_vm_get(man->priv, mem->num_pages << 12, node->page_shift, - NV_MEM_ACCESS_RW, &node->vma[0]); + ret = nouveau_vm_get(man->priv, mem->num_pages << PAGE_SHIFT, + node->page_shift, NV_MEM_ACCESS_RW, &node->vma[0]); if (ret) { kfree(node); Thanks ! Cheers, Ben.

...veau/core/engine/graph/ctxnv108.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c @@ -537,6 +537,7 @@ nv108_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) u32 magic[GPC_MAX][2]; u32 offset; int gpc; + u32 r17e91c, r17e920; mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); @@ -571,8 +572,10 @@ nv108_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) offset += 0x07ff * priv->tpc_nr[gpc]; } - mmio_list(0x17e91c, 0x0b040a0b, 0, 0); - mmio_list(0x1...

...ta structure indicating in which units they are ? > > - Similar confusion arises with things like struct ttm_mem_reg *mem. > For example, in nouveau_ttm.c, I see statements like: > > ret = nouveau_vm_get(man->priv, mem->num_pages << 12, node->page_shift, > NV_MEM_ACCESS_RW, &node->vma[0]); > > Which seems to indicate that mem->num_pages is in multiple of 4k always, > though I would have though that a ttm object was in multiple of > PAGE_SIZE, am I wrong ? > > Especially since the same object is later populated using: > > mem->sta...

...00644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -252,8 +252,8 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man, node->page_shift = 12; - ret = nouveau_vm_get(man->priv, mem->num_pages << 12, node->page_shift, - NV_MEM_ACCESS_RW, &node->vma[0]); + ret = nouveau_vm_get(man->priv, mem->num_pages << PAGE_SHIFT, + node->page_shift, NV_MEM_ACCESS_RW, &node->vma[0]); if (ret) { kfree(node); return ret;

...00644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -252,8 +252,9 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man, node->page_shift = 12; - ret = nouveau_vm_get(man->priv, mem->num_pages << 12, node->page_shift, - NV_MEM_ACCESS_RW, &node->vma[0]); + ret = nouveau_vm_get(man->priv, mem->num_pages << PAGE_SHIFT, + node->page_shift, NV_MEM_ACCESS_RW, + &node->vma[0]); if (ret) { kfree(node); return ret;

...ers/gpu/drm/nouveau/nouveau_ttm.c > > @@ -252,8 +252,8 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man, > > > > node->page_shift = 12; > > > > - ret = nouveau_vm_get(man->priv, mem->num_pages << 12, node->page_shift, > > - NV_MEM_ACCESS_RW, &node->vma[0]); > > + ret = nouveau_vm_get(man->priv, mem->num_pages << PAGE_SHIFT, > > + node->page_shift, NV_MEM_ACCESS_RW, &node->vma[0]); > > if (ret) { > > kfree(node); > > return ret; > > > >

...pages, we will end up doing a null deref in + * nouveau_vm_map_sg. */ + if (WARN_ON(mem->mem_type != TTM_PL_VRAM && !node->pages)) + return -EINVAL; + ret = nouveau_vm_get(nv_client(chan->cli)->vm, mem->num_pages << PAGE_SHIFT, node->page_shift, NV_MEM_ACCESS_RW, vma); -- 1.8.1.5

.../nouveau_ttm.c > +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c > @@ -252,8 +252,8 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man, > > node->page_shift = 12; > > - ret = nouveau_vm_get(man->priv, mem->num_pages << 12, node->page_shift, > - NV_MEM_ACCESS_RW, &node->vma[0]); > + ret = nouveau_vm_get(man->priv, mem->num_pages << PAGE_SHIFT, > + node->page_shift, NV_MEM_ACCESS_RW, &node->vma[0]); > if (ret) { > kfree(node); > return ret; > >

...ivers/gpu/drm/nouveau/nouveau_ttm.c > @@ -252,8 +252,9 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man, > > node->page_shift = 12; > > - ret = nouveau_vm_get(man->priv, mem->num_pages << 12, node->page_shift, > - NV_MEM_ACCESS_RW, &node->vma[0]); > + ret = nouveau_vm_get(man->priv, mem->num_pages << PAGE_SHIFT, > + node->page_shift, NV_MEM_ACCESS_RW, > + &node->vma[0]); Ack. > if (ret) { > kfree(n...

...sernv04.c:124:18: warning: this statement may fall through [-Wimplicit-fallthrough=] Source code is switch (dmaobj->base.access) { case NV_MEM_ACCESS_RO: dmaobj->flags0 |= 0x00004000; break; case NV_MEM_ACCESS_WO: dmaobj->flags0 |= 0x00008000; case NV_MEM_ACCESS_RW: dmaobj->flags2 |= 0x00000002; break; default: return -EINVAL; } Suggest either document the fallthrough or add the missing break. Regards David Binderman

...g, we should find out why and fix it (and have the kernel completely reject such attempts). Ben. > + > ret = nouveau_vm_get(nv_client(chan->cli)->vm, mem->num_pages << > PAGE_SHIFT, node->page_shift, > NV_MEM_ACCESS_RW, vma); > -- > 1.8.1.5 > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel

Hi folks ! So I've been trying to figure out what it would take to make nouveau work properly on architectures where PAGE_SIZE isn't 4k such as most ppc64's. An initial patch from Dave fixed a bogon in nv41.c nv41_vm_map_sg() which was trying to handle the case at that low level, but this isn't enough, and after a bit of digging, I also think that's not the right approach:

...t; > @@ -252,8 +252,8 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man, >> > >> > node->page_shift = 12; >> > >> > - ret = nouveau_vm_get(man->priv, mem->num_pages << 12, node->page_shift, >> > - NV_MEM_ACCESS_RW, &node->vma[0]); >> > + ret = nouveau_vm_get(man->priv, mem->num_pages << PAGE_SHIFT, >> > + node->page_shift, NV_MEM_ACCESS_RW, &node->vma[0]); >> > if (ret) { >> > kfree(node); >> >...

...FT; mem->bus.base = pci_resource_start(dev->pdev, 1); mem->bus.is_iomem = true; if (nv_device(drm->device)->card_type >= NV_50) { struct nouveau_bar *bar = nouveau_bar(drm->device); - struct nouveau_mem *node = mem->mm_node; ret = bar->umap(bar, node, NV_MEM_ACCESS_RW, &node->bar_vma); @@ -1324,6 +1327,7 @@ nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) struct nouveau_bo *nvbo = nouveau_bo(bo); struct nouveau_device *device = nv_device(drm->device); u32 mappable = pci_resource_len(device->pdev, 1) >> PAGE_SHIFT; + i...

...drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c @@ -122,6 +122,7 @@ nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, break; case NV_MEM_ACCESS_WO: dmaobj->flags0 |= 0x00008000; + /* fall through */ case NV_MEM_ACCESS_RW: dmaobj->flags2 |= 0x00000002; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index ad707ff..93493b3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@...

...e fields in those various data structure indicating in which units they are ? - Similar confusion arises with things like struct ttm_mem_reg *mem. For example, in nouveau_ttm.c, I see statements like: ret = nouveau_vm_get(man->priv, mem->num_pages << 12, node->page_shift, NV_MEM_ACCESS_RW, &node->vma[0]); Which seems to indicate that mem->num_pages is in multiple of 4k always, though I would have though that a ttm object was in multiple of PAGE_SIZE, am I wrong ? Especially since the same object is later populated using: mem->start = node->vma[0].offset >&gt...

...de_image = (u32 *)((u8 *)desc + desc->descriptor_size); + for (i = 0; i < (desc->app_start_offset + desc->app_size); i += 4) + nv_wo32(pmu->ucode.obj, i, ucode_image[i/4]); + + /* map allocated memory into GMMU */ + ret = nvkm_gpuobj_map_vm(nv_gpuobj(pmu->ucode.obj), vm, + NV_MEM_ACCESS_RW, &pmu->ucode.vma); + if (ret) + goto map_err; + + nv_debug(ppmu, "%s function end\n", __func__); + return ret; +map_err: + nvkm_gpuobj_destroy(pmu->ucode.obj); +fw_alloc_err: + nvkm_gpuobj_destroy(ppmuvm->pgd); +pgd_alloc_err: + nvkm_gpuobj_destroy(ppmuvm->mem); +instblk_...

...eturn ret; + + ucode_image = (u32 *)((u8 *)desc + desc->descriptor_size); + for (i = 0; i < (desc->app_start_offset + desc->app_size); i += 4) + nv_wo32(priv->ucode.obj, i, ucode_image[i/4]); + + /* map allocated memory into GMMU */ + ret = nvkm_gpuobj_map_vm(priv->ucode.obj, vm, NV_MEM_ACCESS_RW, + &priv->ucode.vma); + if (ret) + return ret; + + return ret; +} + +static int +gk20a_init_pmu_setup_sw(struct gk20a_pmu_priv *priv) +{ + struct nvkm_pmu_priv_vm *pmuvm = &priv->pmuvm; + int ret = 0; + + INIT_WORK(&priv->base.recv.work, gk20a_pmu_process_message); + + ret...