Displaying 20 results from an estimated 253 matches for "nv_error".
2014 Jan 16
2
[PATCH] drm/nv50/graph: add more trap names to print on error
...+ 0x10);
+ u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
+ u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
+ u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
+ int i;
+
+ /* CUDA memory: l[], g[] or stack. */
+ if (ustatus & 0x00000080) {
+ if (e18 & 0x80000000) {
+ /* g[] read fault? */
+ nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
+ tp, e14, e10 | ((e18 >> 24) & 0x1f));
+ e18 &= ~0x1f000000;
+ } else if (e18 & 0xc) {
+ /* g[] write fault? */
+ nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global w...
2009 Dec 27
1
[PATCH] drm/nouveau: create function for "dealing" with gpu lockup
...u/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 84af25c..6438935 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -64,8 +64,7 @@ nouveau_fbcon_sync(struct fb_info *info)
return 0;
if (RING_SPACE(chan, 4)) {
- NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
- info->flags |= FBINFO_HWACCEL_DISABLED;
+ NV_GPU_LOCKUP(info);
return 0;
}
@@ -86,8 +85,7 @@ nouveau_fbcon_sync(struct fb_info *info)
}
if (ret) {
- NV_ERROR(dev, "GPU lockup - switching to software fbcon\n"...
2014 Feb 09
1
[PATCH] drm/nv50/gr: add missing nv_error parameter priv
Commit ea7dce901 ("drm/nv50/gr: print mpc trap name when it's not an mp
trap") added an nv_error call that was missing the priv parameter. This
causes GPFs if the error is ever hit.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Sorry, my bad! But... I hit it and it killed my computer. So things are
probably even.
drivers/gpu/drm/nouveau/core/engine/graph/nv50.c | 2 +-
1 f...
2014 Jan 16
0
[PATCH] drm/nv50/graph: add more trap names to print on error
...u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
> + int i;
> +
> + /* CUDA memory: l[], g[] or stack. */
> + if (ustatus & 0x00000080) {
> + if (e18 & 0x80000000) {
> + /* g[] read fault? */
> + nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
> + tp, e14, e10 | ((e18 >> 24) & 0x1f));
> + e18 &= ~0x1f000000;
> + } else if (e18 & 0xc) {
> +...
2012 Aug 19
1
[PATCH 01/10] drm/nv50: decode PGRAPH status registers on TLB flush fail
...id: %x ", tmp);
+ pr_cont("(0x%08x)\n", status);
+}
+
static int
nv84_graph_tlb_flush(struct nouveau_engine *engine)
{
@@ -219,10 +275,24 @@ nv84_graph_tlb_flush(struct nouveau_engine *engine)
!(timeout = ptimer->read(ptimer) - start > 2000000000));
if (timeout) {
- nv_error(priv, "PGRAPH TLB flush idle timeout fail: "
- "0x%08x 0x%08x 0x%08x 0x%08x\n",
- nv_rd32(priv, 0x400700), nv_rd32(priv, 0x400380),
- nv_rd32(priv, 0x400384), nv_rd32(priv, 0x400388));
+ nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");
+
+ nv_err...
2012 Nov 06
1
[PATCH] drm/nv50: decode PGRAPH status registers on TLB flush fail
...lid: %x ", tmp);
+ pr_cont("(0x%08x) ", status);
+}
+
static int
nv84_graph_tlb_flush(struct nouveau_engine *engine)
{
@@ -219,10 +275,21 @@ nv84_graph_tlb_flush(struct nouveau_engine *engine)
!(timeout = ptimer->read(ptimer) - start > 2000000000));
if (timeout) {
- nv_error(priv, "PGRAPH TLB flush idle timeout fail: "
- "0x%08x 0x%08x 0x%08x 0x%08x\n",
- nv_rd32(priv, 0x400700), nv_rd32(priv, 0x400380),
- nv_rd32(priv, 0x400384), nv_rd32(priv, 0x400388));
+ nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");
+
+ nv_err...
2015 Apr 13
3
[PATCH v4] pmu/gk20a: PMU boot support
...ct nvkm_pmu *pmu = (void *)object;
- struct gk20a_pmu_priv *priv = (void *)pmu;
+ if (enable) {
+ nv_mask(pmc, 0x000200, 0x00002000, 0x00002000);
+ nv_rd32(pmc, 0x00000200);
+ if (nv_wait(priv, 0x0010a10c, 0x00000006, 0x00000000))
+ return 0;
+ nv_mask(pmc, 0x00000200, 0x2000, 0x00000000);
+ nv_error(priv, "Falcon mem scrubbing timeout\n");
+ return -ETIMEDOUT;
+ } else {
+ nv_mask(pmc, 0x00000200, 0x2000, 0x00000000);
+ return 0;
+ }
+}
+static void
+gk20a_pmu_enable_irq(struct gk20a_pmu_priv *priv, struct nvkm_mc *pmc, bool enable)
+{
+ if (enable) {
+ nv_debug(priv, "enabl...
2012 Dec 05
2
[RFC PATCH] drm/nouveau: report channel owner in error messages
...ruct nv04_fifo_priv *priv, u32 chid, u32 get)
{
+ struct nouveau_client *client;
u32 mthd, data;
int ptr;
@@ -421,9 +441,12 @@ nv04_fifo_cache_error(struct nouveau_device *device,
}
if (!nv04_fifo_swmthd(priv, chid, mthd, data)) {
+ client = nv04_fifo_client_for_chid(priv, chid);
+
nv_error(priv,
- "CACHE_ERROR - Ch %d/%d Mthd 0x%04x Data 0x%08x\n",
- chid, (mthd >> 13) & 7, mthd & 0x1ffc, data);
+ "CACHE_ERROR - Ch %d/%d [%s] Mthd 0x%04x Data 0x%08x\n",
+ chid, (mthd >> 13) & 7, client ? client->name : "unk",
+ m...
2015 Apr 08
3
[PATCH V2] pmu/gk20a: PMU boot support.
...a_pmu_enable_hw(struct nvkm_pmu *ppmu, struct nvkm_mc *pmc,
+ bool enable)
+{
+ if (enable) {
+ nv_mask(pmc, 0x000200, 0x00002000, 0x00002000);
+ nv_rd32(pmc, 0x00000200);
+ if (nv_wait(ppmu, 0x0010a10c, 0x00000006, 0x00000000))
+ return 0;
+ nv_mask(pmc, 0x00000200, 0x2000, 0x00000000);
+ nv_error(ppmu, "Falcon mem scrubbing timeout\n");
+ return -ETIMEDOUT;
+ } else {
+ nv_mask(pmc, 0x00000200, 0x2000, 0x00000000);
+ return 0;
+ }
+}
+static void
+pmu_enable_irq(struct nvkm_pmu *ppmu, struct nvkm_mc *pmc, bool enable)
+{
+ if (enable) {
+ nv_debug(ppmu, "enable pmu irq\n&...
2017 Jul 25
1
[PATCH] bios: Restrict missing fp table message to desktop cards.
...@@ static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
struct lvdstableheader lth;
if (bios->fp.fptablepointer == 0x0) {
- /* Apple cards don't have the fp table; the laptops use DDC */
- /* The table is also missing on some x86 IGPs */
-#ifndef __powerpc__
- NV_ERROR(drm, "Pointer to flat panel table invalid\n");
-#endif
+ if (!bios->is_mobile) {
+ /* Most laptop cards lack an fp table. They use DDC.*/
+ NV_ERROR(drm, "Pointer to flat panel table invalid\n");
+ }
+
bios->digital_min_front_porch = 0x4b;
return 0;
}
--
2.1...
2012 Dec 09
0
[PATCH 1/4] drm/nouveau: split fifo interrupt handler
...NV_40) {
+ mthd = nv_rd32(priv, NV04_PFIFO_CACHE1_METHOD(ptr));
+ data = nv_rd32(priv, NV04_PFIFO_CACHE1_DATA(ptr));
+ } else {
+ mthd = nv_rd32(priv, NV40_PFIFO_CACHE1_METHOD(ptr));
+ data = nv_rd32(priv, NV40_PFIFO_CACHE1_DATA(ptr));
+ }
+
+ if (!nv04_fifo_swmthd(priv, chid, mthd, data)) {
+ nv_error(priv,
+ "CACHE_ERROR - Ch %d/%d Mthd 0x%04x Data 0x%08x\n",
+ chid, (mthd >> 13) & 7, mthd & 0x1ffc, data);
+ }
+
+ nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
+ nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
+
+ nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0,
+...
2015 Mar 11
0
[PATCH] pmu/gk20a: PMU boot support.
...>isr_mutex);
> + mutex_init(&pmu->pmu_copy_lock);
> + mutex_init(&pmu->pmu_seq_lock);
> +
> + if (pmufw == NULL) {
> + ret = gk20a_pmu_load_firmware(ppmu, &pmufw);
> + if (ret < 0) {
> + nv_error(ppmu, "failed to load pmu fimware\n");
> + return ret;
> + }
> + nv_debug(ppmu, "loading firmware sucessful\n");
> + ret = gk20a_pmu_init_vm(ppmu, pmufw);
> + if (ret < 0) {
> +...
2015 Mar 11
3
[PATCH] pmu/gk20a: PMU boot support.
...mu = &impl->pmudata;
+
+ nv_subdev(ppmu)->intr = gk20a_pmu_intr;
+
+ mutex_init(&pmu->isr_mutex);
+ mutex_init(&pmu->pmu_copy_lock);
+ mutex_init(&pmu->pmu_seq_lock);
+
+ if (pmufw == NULL) {
+ ret = gk20a_pmu_load_firmware(ppmu, &pmufw);
+ if (ret < 0) {
+ nv_error(ppmu, "failed to load pmu fimware\n");
+ return ret;
+ }
+ nv_debug(ppmu, "loading firmware sucessful\n");
+ ret = gk20a_pmu_init_vm(ppmu, pmufw);
+ if (ret < 0) {
+ nv_error(ppmu, "failed to map pmu fw to va space\n");
+ goto init_vm_err;
+ }
+ }
+ pmu-&...
2009 Dec 19
1
[PATCH] drm/nouveau: always do buffer object moves on bo->channel
...nv50 they allow direct access
+ * to vram. This is needed because we don't know the tiling layout.
+ */
+ vram = NULL;
+ ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
+ 0, nouveau_mem_fb_amount(dev),
+ NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
+ &vram);
+ if (ret) {
+ NV_ERROR(dev, "Error creating direct VRAM ctxdma: %d\n", ret);
+ return ret;
+ }
+
+ ret = nouveau_gpuobj_ref_add(dev, chan, NvDmaVRAM, vram, NULL);
+ if (ret) {
+ NV_ERROR(dev, "Error referencing direct VRAM ctxdma:" \
+ " %d\n", ret);
+ return ret;
+ }
+
+ tt = NULL;
+ r...
2013 Mar 27
3
[PATCH 1/4] drm/nvc0: implement VRAM compression
---
drivers/gpu/drm/nouveau/core/include/subdev/ltcg.h | 7 +
drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c | 55 +++++----
drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c | 129 +++++++++++++++++++-
drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c | 58 +++++++++-
4 files changed, 220 insertions(+), 29 deletions(-)
diff --git
2015 Mar 12
2
[PATCH] pmu/gk20a: PMU boot support.
...>isr_mutex);
> + mutex_init(&pmu->pmu_copy_lock);
> + mutex_init(&pmu->pmu_seq_lock);
> +
> + if (pmufw == NULL) {
> + ret = gk20a_pmu_load_firmware(ppmu, &pmufw);
> + if (ret < 0) {
> + nv_error(ppmu, "failed to load pmu fimware\n");
> + return ret;
> + }
> + nv_debug(ppmu, "loading firmware sucessful\n");
> + ret = gk20a_pmu_init_vm(ppmu, pmufw);
> + if (ret < 0) {
> +...
2015 Apr 30
2
[PATCH v4] pmu/gk20a: PMU boot support
...200, 0x00002000, 0x00002000);
>> + nv_rd32(pmc, 0x00000200);
>> + if (nv_wait(priv, 0x0010a10c, 0x00000006, 0x00000000))
>> + return 0;
>> + nv_mask(pmc, 0x00000200, 0x2000, 0x00000000);
>> + nv_error(priv, "Falcon mem scrubbing timeout\n");
>> + return -ETIMEDOUT;
>> + } else {
>> + nv_mask(pmc, 0x00000200, 0x2000, 0x00000000);
>> + return 0;
>> + }
>> +}
>> +static void
>> +gk20a_pmu...
2012 Aug 19
2
[PATCH 10/10] drm/nouveau: fix off-by-one bugs related to command submission in IB mode
...ers/gpu/drm/nouveau/nouveau_gem.c
@@ -662,7 +662,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
if (unlikely(req->nr_push == 0))
goto out_next;
- if (unlikely(req->nr_push > NOUVEAU_GEM_MAX_PUSH)) {
+ if (unlikely(req->nr_push >= NOUVEAU_GEM_MAX_PUSH)) {
NV_ERROR(drm, "pushbuf push count exceeds limit: %d max %d\n",
req->nr_push, NOUVEAU_GEM_MAX_PUSH);
return nouveau_abi16_put(abi16, -EINVAL);
@@ -718,7 +718,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
}
if (chan->dma.ib_max) {
- ret = nouveau_dma_wait(ch...
2015 May 20
3
[PATCH] ram/gf100-: error out if a ridiculous amount of vram is detected
...u/nvkm/subdev/fb/ramgf100.c
+++ b/drm/nouveau/nvkm/subdev/fb/ramgf100.c
@@ -545,6 +545,12 @@ gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine,
}
}
+ /* if over 1TB of VRAM is reported, something went very wrong, bail */
+ if (ram->size > (1ULL << 40)) {
+ nv_error(pfb, "invalid vram size: %llx\n", ram->size);
+ return -EINVAL;
+ }
+
/* if all controllers have the same amount attached, there's no holes */
if (uniform) {
offset = rsvd_head;
--
2.3.6
2014 Jul 26
5
[PATCH v2 0/3] drm/gk20a: support for reclocking
Second version of the gk20a clock patches. I have tried to keep the therm and
volt devices mandatory in the clock driver, but unfortunately they are too tied
to bios to allow this, at least for the moment. Consequently this version is
mostly a port of the first version to Ben's tree.
Ben, please let me know what I have done wrong in terms of integration to your
tree, as the main purpose of