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...Since there are some holidays expect a small delay. Will let you know by Friday. Thx Sent from my Windows Phone ________________________________ From: Charlie Turner<mailto:charlesturner7c5 at gmail.com> Sent: ‎11/‎11/‎2015 6:34 PM To: Das, Dibyendu<mailto:Dibyendu.Das at amd.com> Cc: nrotem at apple.com<mailto:nrotem at apple.com>; llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] [RFC][SLP] Let's turn -slp-vectorize-hor on by default > I will try to get some spec cpu 2006 rate runs done under -O3 -flto with and without -slp-vect...

Hi Nadav, From: Nadav Rotem <nrotem at apple.com<mailto:nrotem at apple.com>> Date: Monday, 12 August, 2013 1:59 PM To: Paul Redmond <paul.redmond at intel.com<mailto:paul.redmond at intel.com>> Cc: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu>> Subject: Re: [LLVM...

----- Original Message ----- > From: "Joe Abbey" <joe.abbey at gmail.com> > To: "Nadav Rotem" <nrotem at apple.com> > Cc: llvmdev at cs.uiuc.edu > Sent: Saturday, November 17, 2012 1:25:04 PM > Subject: Re: [LLVMdev] [cfe-dev] !!! 3.2 Release branch patching and the Code Owners > > > On Nov 17, 2012, at 12:57 PM, Nadav Rotem <nrotem at apple.com> wrote: > > >...

----- Original Message ----- > From: "Pete Cooper" <peter_cooper at apple.com> > To: "Nadav Rotem" <nrotem at apple.com> > Cc: dag at cray.com, llvmdev at cs.uiuc.edu > Sent: Friday, October 24, 2014 3:40:10 PM > Subject: Re: [LLVMdev] Adding masked vector load and store intrinsics > > On Oct 24, 2014, at 11:38 AM, Nadav Rotem < nrotem at apple.com > wrote: > > I agree wi...

I think that the code owner process is becoming complicated and I am not sure if it serves Chris's original intent. I don't think that we need to change every file nor do we need an automatic tool to find the owner. I think that a simple text file, or a section in the docs is enough. On Nov 17, 2012, at 2:51, Duncan Sands <baldrick at free.fr> wrote: > Hi Pawel, I guess the code

Hi Nadav, On 2013-08-12 12:59 PM, "Nadav Rotem" <nrotem at apple.com> wrote: >Hi Paul, > >You can read about it here: >http://blog.llvm.org/2011/12/llvm-31-vector-changes.html > >> Hi, >> >> I am trying to understand how vector type legalization works. In >>particular, I'm looking at i8 vector types on x8...

On Mar 11, 2013, at 9:41 AM, Nadav Rotem <nrotem at apple.com<mailto:nrotem at apple.com>> wrote: Hi Richard, I did… It originates from an icmp ne <2x i8>, zero initializer followed by a sext of the result 2x i1 to 2x i8. When we visit the SIGN_EXTEND, we generate the ISD::SELECT even though the selector and both operands are v...

...of the vector. In other cases we may want to widen (to the next power of two) and later split in half because the vector is too big. On Aug 12, 2013, at 10:46 AM, Redmond, Paul <paul.redmond at intel.com> wrote: > Hi Nadav, > > On 2013-08-12 12:59 PM, "Nadav Rotem" <nrotem at apple.com> wrote: > >> Hi Paul, >> >> You can read about it here: >> http://blog.llvm.org/2011/12/llvm-31-vector-changes.html >> >>> Hi, >>> >>> I am trying to understand how vector type legalization works. In >>> parti...

At Monday, December 17, 2012 2:05 PM, Nadav Rotem [mailto:nrotem at apple.com] wrote: >This part worries me. The new min/max intrinsics will only be useful if we could pattern match cmp/select into them. Yes, that's the obvious alternative. I don't think we have any strong opinion either way, and fcmp/select is certainly easier to implement. --...

On 5 November 2012 17:41, Nadav Rotem <nrotem at apple.com> wrote: > 1. We do not allow reductions on floating point types. We should allow them when unsafe-math is used. > 2. All of the arrays are located in a struct. At the moment we don't detect that these arrays are disjoin, and this prevents vectorization. Indeed, they look...

> ----- Original Message ----- >> From: "Joe Abbey" <joe.abbey at gmail.com> >> To: "Nadav Rotem" <nrotem at apple.com> >> Cc: llvmdev at cs.uiuc.edu >> Sent: Saturday, November 17, 2012 1:25:04 PM >> Subject: Re: [LLVMdev] [cfe-dev] !!! 3.2 Release branch patching and the Code Owners >> >> >> On Nov 17, 2012, at 12:57 PM, Nadav Rotem <nrotem at apple.com> w...

On May 8, 2013, at 11:07 AM, dag at cray.com wrote: > It might be as simple as adding > an IR-level predicated load and predicated store, I'm not sure. I think that selects on the inputs+outputs of instructions is a good abstraction, and I don't think that we need to add a mask operand to every LLVM IR instruction. However, we do need support for masked load/stores, and I think

...ould be 1) be explicitly specified in AVX2 cost table? Because right now this entry is missing and cost of these operations are taken from BaseTTI (which is generic). IMO, it will make things more clear. Your thoughts on this?? Regards, Suyog Sarda On 4 May 2015 21:57, "Nadav Rotem" <nrotem at apple.com> wrote: > > > On May 4, 2015, at 2:36 AM, suyog sarda <sardask01 at gmail.com> wrote: > > > > Hi all, > > > > I have a query regarding Cost Table for AVX2 in TargetTransformInfo. > > > > The table consist of entries for shift and d...

On Aug 20, 2013, at 10:22 , Nadav Rotem <nrotem at apple.com> wrote: > Can you send the IR of the function ? Attached is the -O0 and -O3 IR -------------- next part -------------- A non-text attachment was scrubbed... Name: vselect_optimized.ll Type: application/octet-stream Size: 1545 bytes Desc: not available URL: <http://lists.l...

> > Line 4501 in trunk DAGCombiner.cpp… I changed the ISD::SELECT to the VT.isVector() ? ISD::VSELECT : ISD::SELECT... > Thanks. From the commit message I think that we should only run this optimization on scalars. >> Can you write down the input SDNode ? What types are inputs ? > > 0x107046d10: v2i8 = vselect 0x107046c10, 0x107046b10, 0x107045e10 [ID=-3]

Done. Best, Anadi. On Thu, Apr 11, 2013 at 7:01 AM, Nadav Rotem <nrotem at apple.com> wrote: > Hi Anadi, > > Yes, this is a bug in the loop vectorizer. The loop vectorizer expects only > one loop counter (integer with step=1). There is no reason why we should > not handle the case below, and it should be easy to fix. Interestingly > enough if you...

Hi, Last week I wrote llvm-dev and presented data that shows how enabling the vectorizer on -Os can improve the performance of many workloads and that it has negligible effects on code size. I also added a command line switch to make it easier for people to benchmark the vectorizer using -Os directly from clang without changing LLVM. Has anyone done any benchmarks on -Os + vectorization ?

I will try to get some spec cpu 2006 rate runs done under -O3 -flto with and without -slp-vectorize-hor and let you know. -Thx -----Original Message----- From: nrotem at apple.com [mailto:nrotem at apple.com] Sent: Tuesday, November 10, 2015 3:33 AM To: Charlie Turner Cc: Das, Dibyendu; llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] [RFC][SLP] Let's turn -slp-vectorize-hor on by default > On Nov 9, 2015, at 9:55 AM, Charlie Turner via llvm-dev <...

On 30 October 2013 09:25, Nadav Rotem <nrotem at apple.com> wrote: > The access pattern to arrays a and b is non-linear. Unrolled loops are > usually handled by the SLP-vectorizer. Are ir0 and ir1 consecutive for all > values for i ? > Based on his list of values, it seems that the induction stride is linear within each bloc...

...and in what benchmarks/apps ? > > > > *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of *David > Callahan via llvm-dev > *Sent:* Monday, August 01, 2016 11:15 PM > *To:* LLVM Dev Mailing list <llvm-dev at lists.llvm.org> > *Cc:* Nadav Rotem <nrotem at fb.com> > *Subject:* [llvm-dev] [LLVM] New Dead Code Elimination > > > > I have a rewrite of the aggressive dead code elimination pass which > handles control flow and allows may-be-infinite loops to be removed under > optional flag. Chandler suggested rather than a large...