search for: nouveau_gpuobj_ref

...eau_bar_alloc; > - priv->base.kmap = nvc0_bar_kmap; > priv->base.umap = nvc0_bar_umap; > priv->base.unmap = nvc0_bar_unmap; > priv->base.flush = nv84_bar_flush; > @@ -176,12 +177,16 @@ nvc0_bar_dtor(struct nouveau_object *object) > nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd); > nouveau_gpuobj_ref(NULL, &priv->bar[1].mem); > > - if (priv->bar[0].vm) { > - nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]); > - nouveau_vm_ref(NULL, &priv->bar[0].vm,...

...esource_len(device, 1) - 1)); - - priv->base.alloc = nouveau_bar_alloc; - priv->base.kmap = nvc0_bar_kmap; priv->base.umap = nvc0_bar_umap; priv->base.unmap = nvc0_bar_unmap; priv->base.flush = nv84_bar_flush; @@ -176,12 +177,16 @@ nvc0_bar_dtor(struct nouveau_object *object) nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd); nouveau_gpuobj_ref(NULL, &priv->bar[1].mem); - if (priv->bar[0].vm) { - nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]); - nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd); + if (priv->bar[0].mem) { + if (pri...

...(vmm)->mutex); - nouveau_vm_ref(NULL, &vma->vm, NULL); + vma->vm = NULL; + ref = --vm->refcount; + mutex_unlock(&nv_subdev(vmm)->mutex); + if (!ref) + nouveau_vm_del(vm); } int @@ -429,25 +434,21 @@ nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd) nouveau_gpuobj_ref(pgd, &vpgd->obj); - mutex_lock(&nv_subdev(vmm)->mutex); for (i = vm->fpde; i <= vm->lpde; i++) vmm->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj); list_add(&vpgd->head, &vm->pgd_list); - mutex_unlock(&nv_subdev(vmm)->mutex); return 0; }...

Hello everyone, GK20A is the Kepler-based GPU used in the upcoming Tegra K1 chips. The following patches perform architectural changes to Nouveau that are necessary to support non-PCI GPUs and add initial support for GK20A. Although the support is still very basic and more user-space changes will be needed to make the full graphics stack run on top of it, we were able to successfully open

...hannel *chan) if (ret) return ret; + /* Allocate what we need for (simple) cross channel synchronisation. */ + if (dev_priv->card_type >= NV_50) { + struct nouveau_gpuobj *nvsw = NULL; + + ret = nouveau_gpuobj_sw_new(chan, NV50_NVSW, &nvsw); + if (ret) + return ret; + + ret = nouveau_gpuobj_ref_add(dev, chan, NvSw, nvsw, NULL); + if (ret) + return ret; + + ret = nouveau_notifier_alloc(chan, NvNotify1, 32, &chan->sync_ntfy); + if (ret) + return ret; + } + /* Map push buffer */ ret = nouveau_bo_map(chan->pushbuf_bo); if (ret) @@ -87,6 +104,15 @@ nouveau_dma_init(struc...

...EN */ + + return 0; +} + +static int +nv84_bsp_fini(struct nouveau_object *object, bool suspend) +{ + struct nouveau_device *device = nv_device(object); + struct nv84_bsp_priv *priv = (void *)object; + + nv_wr32(device, 0x103d84, 0); /* INTR_EN */ + nv_wr32(device, 0x103d94, 0); /* FIFO_CTRL */ + + nouveau_gpuobj_ref(NULL, &priv->gpu_fw); + + return nouveau_engine_fini(&priv->base, suspend); +} + struct nouveau_oclass nv84_bsp_oclass = { .handle = NV_ENGINE(BSP, 0x84), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nv84_bsp_ctor, - .dtor = _nouveau_engine_dtor, - .init = _nouveau_engi...

...@@ nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan) return ret; } - ret = drm_mm_init(&chan->ramin_heap, base, size); + ret = drm_mm_init(&chan->ramin_heap, base, size - base); if (ret) { NV_ERROR(dev, "Error creating PRAMIN heap: %d\n", ret); nouveau_gpuobj_ref(NULL, &chan->ramin); -- 1.7.7.1

...w->data, fw->size, GFP_KERNEL); + falcon->code.data = vmemdup(fw->data, fw->size); falcon->code.size = fw->size; release_firmware(fw); if (!falcon->code.data) @@ -235,8 +245,8 @@ _nouveau_falcon_fini(struct nouveau_object *object, bool suspend) if (!suspend) { nouveau_gpuobj_ref(NULL, &falcon->core); if (falcon->external) { - kfree(falcon->data.data); - kfree(falcon->code.data); + vfree(falcon->data.data); + vfree(falcon->code.data); falcon->code.data = NULL; } } -- 1.8.3.2

- Depth and stencil buffers are supposed to be large enough in general. Signed-off-by: Maarten Maathuis <madman2003 at gmail.com> --- drivers/gpu/drm/nouveau/nouveau_bo.c | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index e342a41..9fc4bd6 100644 ---

...ect *object, bool suspend) > +{ > + struct nouveau_device *device = nv_device(object); > + struct nv84_bsp_priv *priv = (void *)object; > + > + nv_wr32(device, 0x103d84, 0); /* INTR_EN */ > + nv_wr32(device, 0x103d94, 0); /* FIFO_CTRL */ > + > + nouveau_gpuobj_ref(NULL, &priv->gpu_fw); > + > + return nouveau_engine_fini(&priv->base, suspend); > +} > + > struct nouveau_oclass > nv84_bsp_oclass = { > .handle = NV_ENGINE(BSP, 0x84), > .ofuncs = &(struct nouveau_ofuncs) { > .cto...

- In the current situation the padding that is added is dangerous to write to, userspace could potentially overwrite parts of another bo. - Depth and stencil buffers are supposed to be large enough in general so the waste of memory should be acceptable. - Alternatives are hiding the padding from users or splitting vram into 2 zones. Signed-off-by: Maarten Maathuis <madman2003 at gmail.com>

...3f); /* INTR */ + nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ + + return 0; +} + +int +_nouveau_xtensa_fini(struct nouveau_object *object, bool suspend) +{ + struct nouveau_xtensa *xtensa = (void *)object; + + nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */ + nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */ + + nouveau_gpuobj_ref(NULL, &xtensa->gpu_fw); + + return nouveau_engine_fini(&xtensa->base, suspend); +} diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c index 1d9f614..ee4cff1 100644 --- a/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c +++ b/driv...