search for: nouveau_gpuobj_new

...localhost [drm:drm_sg_alloc] drm_sg_alloc Aug 6 21:11:46 localhost [drm:drm_sg_alloc] sg size=16777216 pages=4096 Aug 6 21:11:46 localhost [drm:drm_sg_alloc] sg alloc handle = 15f7d200 Aug 6 21:11:46 localhost [drm:drm_sg_alloc] sg alloc virtual = ffffc20015f81000 Aug 6 21:11:46 localhost [drm:nouveau_gpuobj_new_fake] offset=0x00010000 size=0x00000200 flags=0x00000003 Aug 6 21:11:46 localhost [drm:nouveau_gpuobj_new_fake] gpuobj ffff81003a5a19c0 Aug 6 21:11:46 localhost [drm:nv40_graph_init] Loading context-switch voodoo Aug 6 21:11:46 localhost [drm:nouveau_fifo_init] Setting defaults for remaining PFI...

...ouveau_vm *vm; > + resource_size_t bar_len; > int ret; > > - ret = nouveau_bar_create(parent, engine, oclass, &priv); > - *pobject = nv_object(priv); > - if (ret) > - return ret; > - > - /* BAR3 */ > ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, > - &priv->bar[0].mem); > - mem = priv->bar[0].mem; > + &priv->bar[nr].mem); > + mem = priv->bar[nr].mem; > if (ret) > return re...

...struct nouveau_device *device = nv_device(&priv->base); struct nouveau_gpuobj *mem; struct nouveau_vm *vm; + resource_size_t bar_len; int ret; - ret = nouveau_bar_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - /* BAR3 */ ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, - &priv->bar[0].mem); - mem = priv->bar[0].mem; + &priv->bar[nr].mem); + mem = priv->bar[nr].mem; if (ret) return ret; ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0, - &priv->bar[0].pgd); + &priv...

...struct nouveau_device *device = nv_device(&priv->base); struct nouveau_gpuobj *mem; struct nouveau_vm *vm; + resource_size_t bar_len; int ret; - ret = nouveau_bar_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - /* BAR3 */ ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, - &priv->bar[0].mem); - mem = priv->bar[0].mem; + &priv->bar[nr].mem); + mem = priv->bar[nr].mem; if (ret) return ret; ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0, - &priv->bar[0].pgd); + &priv...

...- insert ch0 0x000000f0: h=0x8000000e, c=0x80000004 [ 13.271499] [drm] nouveau 0000:01:00.0: nouveau_gpuobj_dma_new:679 - ch0 class=0x003d offset=0x40000 size=0x20 [ 13.271499] [drm] nouveau 0000:01:00.0: nouveau_gpuobj_dma_new:680 - access=0 target=0 [ 13.271499] [drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:216 - ch0 size=16 align=16 flags=0x00000006 [ 13.271499] [drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:224 - gpuobj ffff88000219ac60 [ 13.271499] [drm] nouveau 0000:01:00.0: nouveau_gpuobj_new:241 - global heap fallback [ 13.271499] [drm] nouveau 0000:01:00.0: nouveau_gpuobj_ref_add:457 - ch...

...vc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, > - struct nouveau_oclass *oclass, void *data, u32 size, > - struct nouveau_object **pobject) > +nvc0_bar_init_vm(struct nvc0_bar_priv *priv, int nr, int bar) > { [...] > - /* BAR3 */ > ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, > - &priv->bar[0].mem); > - mem = priv->bar[0].mem; > + &priv->bar[nr].mem); > + mem = priv->bar[nr].mem; > if (ret) > return ret; > > ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0, > -...

...nouveau_abi16_swclass(drm), NULL, 0, &object); > if (ret == 0) { > @@ -234,6 +238,7 @@ nouveau_accel_init(struct nouveau_drm *drm) > return; > } > > +skip_sw_init: > if (device->card_type < NV_C0) { > ret = nouveau_gpuobj_new(drm->device, NULL, 32, 0, 0, > &drm->notify); > -- > 1.9.2 > > _______________________________________________ > Nouveau mailing list > Nouveau at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/nouveau

...engine/xtensa.c b/drivers/gpu/drm/nouveau/core/engine/xtensa.c index 0639bc5..5f6ede7 100644 --- a/drivers/gpu/drm/nouveau/core/engine/xtensa.c +++ b/drivers/gpu/drm/nouveau/core/engine/xtensa.c @@ -118,7 +118,13 @@ _nouveau_xtensa_init(struct nouveau_object *object) return ret; } - ret = nouveau_gpuobj_new(object, NULL, fw->size, 0x1000, 0, + if (fw->size > 0x40000) { + nv_warn(xtensa, "firmware %s too large\n", name); + release_firmware(fw); + return -EINVAL; + } + + ret = nouveau_gpuobj_new(object, NULL, 0x40000, 0x1000, 0, &xtensa->gpu_fw); if (ret) {...

...rm/nouveau/core/engine/fifo/nve0.c index 54c1b5b..dbc3ff6 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c @@ -852,8 +852,8 @@ nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return ret; } - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 4096 * 0x200, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem); + ret = nouveau_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem); if (ret) return ret; -- 1.8.5.3

.../core/engine/fifo/nve0.c index 9a850fe19515..99c9deea248f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c @@ -852,8 +852,8 @@ nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return ret; } - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 4096 * 0x200, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem); + ret = nouveau_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem); if (ret) return ret; -- 1.8.5.4

Hi everyone, Way overdue v2 of the final patches that enable basic GK20A support. Hopefully all the issues raised with v1 have been addressed. Changes since v1: - Use gk20a clock driver by Ben instead of twiddling nv04's - Name new classes after gk20a instead of nvea - Addressed comments about BAR initialization code factorization - Removed non-essential code which only purpose was to avoid

Hello everyone, GK20A is the Kepler-based GPU used in the upcoming Tegra K1 chips. The following patches perform architectural changes to Nouveau that are necessary to support non-PCI GPUs and add initial support for GK20A. Although the support is still very basic and more user-space changes will be needed to make the full graphics stack run on top of it, we were able to successfully open

Hi everyone, Here is the second batch of patches to add GK20A support to Nouveau. This time we are adding the actual chip support, and this series brings the driver to a point where a slightly-tweaked Mesa successfully runs shaders and renders triangles on GBM! Many thanks to Thierry Reding and the people on the #nouveau IRC channel for their help without which we would not have reached this

Latest patches for GK20A, taking comments received for v3 into account. Changes since v3: - use only pfn_to_page() and page_to_pfn() in GK20A's FB. These functions are present on every arch and the physical address to page frame number conversion is also consistently a shift of PAGE_SHIFT. This part will probably be replaced by something nicer in the future anyway. - fixed a warning on

..._sw_init; + ret = nouveau_object_new(nv_object(drm), NVDRM_CHAN, NVDRM_NVSW, nouveau_abi16_swclass(drm), NULL, 0, &object); if (ret == 0) { @@ -233,6 +242,7 @@ nouveau_accel_init(struct nouveau_drm *drm) return; } +skip_sw_init: if (device->card_type < NV_C0) { ret = nouveau_gpuobj_new(drm->device, NULL, 32, 0, 0, &drm->notify); -- 1.8.5.3

..._sw_init; + ret = nouveau_object_new(nv_object(drm), NVDRM_CHAN, NVDRM_NVSW, nouveau_abi16_swclass(drm), NULL, 0, &object); if (ret == 0) { @@ -233,6 +242,7 @@ nouveau_accel_init(struct nouveau_drm *drm) return; } +skip_sw_init: if (device->card_type < NV_C0) { ret = nouveau_gpuobj_new(drm->device, NULL, 32, 0, 0, &drm->notify); -- 1.9.1

..._sw_init; + ret = nouveau_object_new(nv_object(drm), NVDRM_CHAN, NVDRM_NVSW, nouveau_abi16_swclass(drm), NULL, 0, &object); if (ret == 0) { @@ -234,6 +238,7 @@ nouveau_accel_init(struct nouveau_drm *drm) return; } +skip_sw_init: if (device->card_type < NV_C0) { ret = nouveau_gpuobj_new(drm->device, NULL, 32, 0, 0, &drm->notify); -- 1.9.2

...v84_bsp_init(struct nouveau_object *object) +{ + struct nouveau_device *device = nv_device(object); + struct nv84_bsp_priv *priv = (void *)object; + int i, ret; + u32 tmp; + + if (!priv->fw) + return -EINVAL; + + ret = nouveau_engine_init(&priv->base); + if (ret) + return ret; + + ret = nouveau_gpuobj_new(object, NULL, 0x40000, 0x1000, 0, + &priv->gpu_fw); + if (ret) + return ret; + + tmp = nv_rd32(device, 0x103c20); /* INTR */ + if (tmp) + nv_warn(priv, "Unexpected read from XTENSA.INTR: 0x%x", tmp); + + nv_wr32(device, 0x103d10, 0x1fffffff); /* ?? */ + nv_wr32(device, 0x103d...

Changes since v2: - Enabled software class - Removed unneeded changes to nouveau_accel_init() - Replaced use of architecture-private pfn_to_dma() and dma_to_pfn() with the portable page_to_phys()/phys_to_page() - Fixed incorrect comment/commit log talking about bytes instead of words Hope this looks good! Once this gets merged the next set will be to use this driver on Jetson and Venice2

Hi, Please find attached the patches which I currently use on my desktop machine for dual head with the randr branch to fix the issues which I found. They may help others as well but may e.g. also disable the Xv blitter which might be working for some (but didn't on my card) - more information is found in the text comments in the patches. I have to hurry so this is short, will be back.