search for: noregister

Hi all, what is exactly "zero_reg"? from ARMInstFromats.td: *def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> {...}* I thought zero_reg can be replace by a random name like (alu_stat_reg for alu state register) but when I compiled it, I figure out that zero_reg is a predefined variable. Can someone please give me more information about

...gt; implement conditional branching.  There is a register class for predicates > (i1 in LLVM) and all machine instructions have a predicate operand and > predicate filter (PTX supports inverted predicates).  For un-predicated > instructions, the predicate operand is just set to the special NoRegister > constant. > >> >> Thanks, Roy. >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > > > -- > &g...

...urrently use it to implement conditional branching. There is a register class for predicates (i1 in LLVM) and all machine instructions have a predicate operand and predicate filter (PTX supports inverted predicates). For un-predicated instructions, the predicate operand is just set to the special NoRegister constant. > > Thanks, Roy. > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > -- Thanks, Justin Holewinski -------------- next pa...

...in <YourTarget>GenRegisterInfo.inc. These numbers don't have any meaning other than to represent a particular register. The 0x01 would be the encoding used in generating the binary. The D0 has id 14 on ARM because there are 13 other registers preceding it: namespace ARM { enum { NoRegister, APSR = 1, APSR_NZCV = 2, CPSR = 3, FPEXC = 4, FPINST = 5, FPSCR = 6, FPSCR_NZCV = 7, FPSID = 8, ITSTATE = 9, LR = 10, PC = 11, SP = 12, SPSR = 13, D0 = 14, ... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted b...

...ional branching. There is a register class for > predicates > > (i1 in LLVM) and all machine instructions have a predicate operand and > > predicate filter (PTX supports inverted predicates). For un-predicated > > instructions, the predicate operand is just set to the special NoRegister > > constant. > > > >> > >> Thanks, Roy. > >> _______________________________________________ > >> LLVM Developers mailing list > >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > >> http://lists.cs.uiuc.edu/mailman/listinf...

...you're not actually using the landingpad's exception selector nor, if I understand " This is enough to support the gc.statepoint work " correctly, its exception pointer, it's possible that TLI.getExceptionPointerRegister and TLI.getExceptionSelectorRegister should be returning NoRegister for your personality. That would require modifying the EHPersonality enum and corresponding string matching in Analysis/EHPersonalities.h to recognize your personality, but I think that would be fine (it highlights a potential scaling issue if we add lots of targets that each need this, but that...

...you're not actually using the landingpad's exception selector nor, if I understand " This is enough to support the gc.statepoint work " correctly, its exception pointer, it's possible that TLI.getExceptionPointerRegister and TLI.getExceptionSelectorRegister should be returning NoRegister for your personality. That would require modifying the EHPersonality enum and corresponding string matching in Analysis/EHPersonalities.h to recognize your personality, but I think that would be fine (it highlights a potential scaling issue if we add lots of targets that each need this, but that...

Hi, I was wondering if LLVM supports predicates and conditional execution. Something like we have in IA64. There is a register class of predicates and then every instruction may be predicated by a register from this class. For example: cmp_less p, x, y // p is a predicate which gets the result of x < y p add x, x, 2 // if p then do the add instruction Is there support in LLVM to something

Dear all, in my TestRegisterInfo.td file, I defined a register like this: class TestReg<bits<6> enc, string name> : Register<name> { let HWEncoding{5-0} = enc; let Namespace = "TEST"; } def D0 : TestReg<0x01, "d0">, DwarfRegNum<[1]>; but when I compile, the result I have in TestGenAsmMatcher.inc is this: case 'd': // 7

...<[32]>; def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; So R2:R3 are subregs of D1. These definitions are mapped to HexagonGenRegisterInfo.inc in something like this: enum { NoRegister, D0 = 1, D1 = 2, D2 = 3, D3 = 4, D4 = 5, ... R0 = 27, R1 = 28, R2 = 29, R3 = 30, R4 = 31, ... NUM_TARGET_REGS // 62 }; On the other end of the problem, I use the following to iterate over sub-regs of (in this case) D1: for (MCRegUnitIterator Units(Reg, &TRI); Units.isV...

...quot;r3:2", [R2, R3]>, DwarfRegNum<[34]>; > def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; > > So R2:R3 are subregs of D1. > > These definitions are mapped to HexagonGenRegisterInfo.inc in something like > this: > enum { > NoRegister, > D0 = 1, > D1 = 2, > D2 = 3, > D3 = 4, > D4 = 5, > ... > R0 = 27, > R1 = 28, > R2 = 29, > R3 = 30, > R4 = 31, > ... > NUM_TARGET_REGS // 62 > }; > > On the other end of the problem, I use the following to iterate over > su...

Are you asking what the parsing rules are, or how you should modify the LLVM code to achieve that result? If the latter, you haven’t really given enough detail here. What code, exactly, have you tried modifying? Do you have any ideas for how it could work? -Eli From: Eric Astor <epastor at google.com> Sent: Tuesday, January 21, 2020 2:44 PM To: Eli Friedman <efriedma at

The company I work for uses quiet some ARM processors and I am trying to convince them to let me spend some company time building an llvm back end :-) I have read the documentation and taken a look on the X86 back end. It looks quiet simple to get a very minimal back end working. I am considering for a first version: 1) only support the 32 bits ABI 2) Ignore the shifter (i.e use only 8 bits

> On Dec 1, 2015, at 11:14 PM, David Majnemer <david.majnemer at gmail.com> wrote: > > While we support 'opaque' types nested within struct types, they are not exactly battle tested: > > $ cat t.ll > %opaque_ty = type opaque > > %struct_ty = type { i32, %opaque_ty } > > define %struct_ty @f(%struct_ty* %p) { > %load = load %struct_ty,

...4]>; > > def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; > > > > So R2:R3 are subregs of D1. > > > > These definitions are mapped to HexagonGenRegisterInfo.inc in > > something like > > this: > > enum { > > NoRegister, > > D0 = 1, > > D1 = 2, > > D2 = 3, > > D3 = 4, > > D4 = 5, > > ... > > R0 = 27, > > R1 = 28, > > R2 = 29, > > R3 = 30, > > R4 = 31, > > ... > > NUM_TARGET_REGS // 62 > > }; > > > &...

Andy, Lang, Thanks for the suggestion. I have spent more time with it today, and I do see some strange things in liveness update. I am not at the actual cause yet, but here is what I got so far: I have the following live ranges when I start scheduling a region: R2 = [0B,48r:0)[352r,416r:5)... R3 = [0B,48r:0)[368r,416r:5)... R4 = [0B,32r:0)[384r,416r:4)... R5 = [0B,32r:0)[400r,416r:4)...