search for: nopl

Hi This patch fixes code generation bug - 586-class CPUs don't support the nopl instruction and some 686-class CPUs don't support it too. I created bug 17792 for that. BTW. I think you should also optimize padding on these CPUs - instead of a stream of 0x90 nops, you should generate variants of "lea (%esi), %esi" instruction like gcc. This patch disables g...

Please include a testcase with the patch. gas uses " nopl 0x0(%eax)" for k6_2. Are you sure it is a gas bug? On 3 November 2013 13:50, Mikulas Patocka <mikulas at artax.karlin.mff.cuni.cz> wrote: > Hi > > This patch fixes code generation bug - 586-class CPUs don't support the > nopl instruction and some 686-class CPUs don'...

On Tue, 5 Nov 2013, Rafael Espíndola wrote: > Please include a testcase with the patch. I'm sending testcase here. Compile it with "clang -O2 -march=k6-2 -c loop.c" > gas uses " nopl 0x0(%eax)" for k6_2. Are you sure it is a gas bug? Yes, it is gas bug. I should report it to binutils maintainers. Mikulas > On 3 November 2013 13:50, Mikulas Patocka > <mikulas at artax.karlin.mff.cuni.cz> wrote: > > Hi > > > > This patch fixes code generati...

...I'm sending testcase here. Compile it with > "clang -O2 -march=k6-2 -c loop.c" The test should be in the patch itself. It can use llvm-mc to check how the nops are expanded. The trick used by MachO/x86_32-optimal_nop.s is to use '.align X, 0x90'. >> gas uses " nopl 0x0(%eax)" for k6_2. Are you sure it is a gas bug? > > Yes, it is gas bug. I should report it to binutils maintainers. Thanks! Cheers, Rafael

...lvm-mc to check > how the nops are expanded. The trick used by > MachO/x86_32-optimal_nop.s is to use '.align X, 0x90'. So put it there and commit it to llvm codebase. I'm not an expert in llvm, I just needed a patch to make it work on my computer. > >> gas uses " nopl 0x0(%eax)" for k6_2. Are you sure it is a gas bug? > > > > Yes, it is gas bug. I should report it to binutils maintainers. > > Thanks! > > Cheers, > Rafael I already reported it to binutils maintainers and they fixed it. Mikulas

...z at infradead.org wrote: > > Shouldn't we __always_inline those? They're going to be really small. > > I can send a v2, and you can choose. For reference, though: > > ffffffff86271ee0 <arch_local_save_flags>: > ffffffff86271ee0: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) > ffffffff86271ee5: 48 83 3d 43 87 e4 01 cmpq $0x0,0x1e48743(%rip) # ffffffff880ba630 <pv_ops+0x120> > ffffffff86271eec: 00 > ffffffff86271eed: 74 0d je ffffffff86271efc <arch_local_save_flags+0x1c> >...

...z at infradead.org wrote: > > Shouldn't we __always_inline those? They're going to be really small. > > I can send a v2, and you can choose. For reference, though: > > ffffffff86271ee0 <arch_local_save_flags>: > ffffffff86271ee0: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) > ffffffff86271ee5: 48 83 3d 43 87 e4 01 cmpq $0x0,0x1e48743(%rip) # ffffffff880ba630 <pv_ops+0x120> > ffffffff86271eec: 00 > ffffffff86271eed: 74 0d je ffffffff86271efc <arch_local_save_flags+0x1c> >...

Chris Webb <chris at arachsys.com> wrote: > My CPU flags inside the crashing guest look like this: > > fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush > mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl > extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave > avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse > 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 > > whereas in a (working) -cpu qemu64 guest, they look...

Chris Webb <chris at arachsys.com> wrote: > My CPU flags inside the crashing guest look like this: > > fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush > mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl > extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave > avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse > 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 > > whereas in a (working) -cpu qemu64 guest, they look...

...nning with -smp 1 instead of -smp 4. (Removing/changing the -machine q35 makes no difference.) My CPU flags inside the crashing guest look like this: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 whereas in a (working) -cpu qemu64 guest, they look like this: fpu de pse t...

...nning with -smp 1 instead of -smp 4. (Removing/changing the -machine q35 makes no difference.) My CPU flags inside the crashing guest look like this: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 whereas in a (working) -cpu qemu64 guest, they look like this: fpu de pse t...

...pu cores : 4 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm ida arat epb xsaveopt pln pts dtherm tpr_shadow vnmi flexpriority ept vpid fsgsbase...

...cid : 7 > fpu : yes > fpu_exception : yes > cpuid level : 13 > wp : yes > flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat > pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb > rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology > nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx > est tm2 ssse3 fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt > tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm ida arat epb > xsaveopt pln pts dtherm tpr_shadow vnmi flexpriorit...

...ing output, VT-d extensions are supported also: root at lapdev01:~# cat /proc/cpuinfo | grep vmx flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 fma cx16 xtpr pdcm pcid sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm ida arat epb pln pts dtherm tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2...

...code into a file after implementing notifyObjectCompiled method. IrExprGetValue: 0x00007fe4cc6c2000: push %rbp 0x00007fe4cc6c2001: mov %rsp,%rbp 0x00007fe4cc6c2004: mov 0x10(%rdi),%rax 0x00007fe4cc6c2008: pop %rbp 0x00007fe4cc6c2009: jmpq *%rax 0x00007fe4cc6c200b: nopl 0x0(%rax,%rax,1) JittedOpExpr: 0x00007fe4cc6c2010: push %rbp 0x00007fe4cc6c2011: mov %rsp,%rbp *0x00007fe4cc6c2014: movabs $0x7fe4801fa1f8,%rax* 0x00007fe4cc6c201e: movabs $0x7fe4801fa1e8,%rdi 0x00007fe4cc6c2028: callq *(%rax) 0x00007fe4cc6c202a: add $0x5,%rax 0x0000...

...1 microcode : 0x1 cpu MHz : 1995.144 cache size : 4096 KB fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx rdtscp lm constant_tsc rep_good nopl eagerfpu pni pclmulqdq ssse3 cx16 pcid sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer aes xsave avx hypervisor lahf_lm xsaveopt bogomips : 4105.33 clflush size : 64 cache_alignment : 64 address sizes : 46 bits physical, 48 bits virtual power management: <capabilities> <host...

...picid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 1 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt lm 3dnowext 3dnow rep_good nopl pni lahf_lm cmp_legacy bogomips : 2249.99 TLB size : 1024 4K pages clflush size : 64 cache_alignment : 64 address sizes : 40 bits physical, 48 bits virtual power management: ts fid vid ttp so the same for core id 1 ? i think this processor has AMD-V support. the mainboard is as...

...;chris at arachsys.com> wrote: >> >>> My CPU flags inside the crashing guest look like this: >>> >>> fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush >>> mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl >>> extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave >>> avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse >>> 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 >>> >>> whereas in...

...;chris at arachsys.com> wrote: >> >>> My CPU flags inside the crashing guest look like this: >>> >>> fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush >>> mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl >>> extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave >>> avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse >>> 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 >>> >>> whereas in...

I did a yum update on my management server and now the ovirt gui is no longer accessable. Is it supposed to just work or do I need to do something after the yum update? Justin.