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Hi, I think there are a set of typos in the ATOMIC_LOAD_UMIN_I* and ATOMIC_LOAD_UMAX_I* pseudo-instructions . Specifically, def ATOMIC_LOAD_MIN_I32 : PseudoInst< (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>; and def ATOMIC_LOAD_UMIN_I32 : PseudoInst< (outs

Thanks. Fixed with r147032. Evan On Dec 16, 2011, at 1:50 AM, George Russell wrote: > Hi, > > I think there are a set of typos in the ATOMIC_LOAD_UMIN_I* and > ATOMIC_LOAD_UMAX_I* > pseudo-instructions . > > Specifically, > > def ATOMIC_LOAD_MIN_I32 : PseudoInst< > (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, >

Hi Evan, The problem repeats with the i8 and i16 variants, as well. Cheers, George On 21/12/2011 04:07, Evan Cheng wrote: > Thanks. Fixed with r147032. > > Evan > > On Dec 16, 2011, at 1:50 AM, George Russell wrote: > >> Hi, >> >> I think there are a set of typos in the ATOMIC_LOAD_UMIN_I* and >> ATOMIC_LOAD_UMAX_I* >> pseudo-instructions .

Hello. I have problems specifying vector instructions with immediate values in TableGen. I wrote the following specification (I got inspired from the MSA vector instructions for the Mips back end): class MSA_I16_FMT<bits<9> opcode>: MSAInst { bits<16> s16; let Inst{31-23} = opcode; let Inst{26-11} = s16; }

Hi, I'm trying to complete the lowering for a new microcontroller. I'm using LLVM 3.8. For now this lowering crashes on 'Store' node, which is actually not yet defined. I've tried to map the ISel 'Store' node to architecture specific instructions. I've define the following semantic to my architecture specific instructions: def MOVSUTO_SU_rr :

Hello, I'm trying to define in my new back end, in MyBackendInstrInfo.td file, a vector load instruction that takes an immediate address operand. (I got inspired from Mips' MSA SIMD extensions.) Could you please tell me what's the right way to do it? Here, the load class has $addrsrc which is a relative address with base a certain register and offset: class

Hello, I’m a newbie here, working on a project to enforce Control Flow Integrity (CFI) on programs compiled with LLVM. We’re using LLVM 3.3 so we can leverage poolalloc's dsa analysis. Ideally this will be as target-independent as possible, but our primary target is ARM. One of our passes requires inserting different i32 IDs at various points into the code we’re compiling. As far as I can

Hello. I have extended the BPF back end with vector registers (inspiring from Mips MSA) - something like this: def MSA128D: RegisterClass<"Connex", [v128i16], 32, (sequence "Wh%u", 0, 31)>; I also added vector store and load instructions in the style of Mips MSA - see

Dear all. I have a problem with the following situation: I want to handle an intrinsic function in a specific way. The prototype of my function is: "/int my_intrinsic_name()/" So I want to generate a move instruction which should use two register type operands: "/mov R1, R2/" For this purpose I assume that the instruction definition in the TargetInstrInfo.td file

Hi, For the development of a new micro-controller backend, I try to lowering the following store SDNode: t5: ch = store<ST2[%ptr2](align=4)> t0, Constant:i16<3>, FrameIndex:i16<1>, undef:i16 I have defined the following instruction and associated DAG pattern. def MOVSUTO_A_i32o : CLPFPU_A_i32o_Inst<0b1000001101,

Hi, I'm try to lower the store LLVM-IR instruction as per the following LLVM IR program: *** IR Dump After Module Verifier *** define void @storeloadi32() { %ptr = alloca i32 store volatile i32 12, i32* %ptr ret void } The target instruction is associated to the store like this: def MOVSUTO_A_iSLr : CLPFPU_A_iSLr<0b1000001101,

Spills created at the end of the block (I assume you mean what fast regalloc does at -O0) are created long after instruction selection. In that case it sounds like your implementation of storeRegToStackSlot/loadRegFromStackSlot is broken -Matt On Tue, Oct 25, 2016 at 7:30 AM +0800, "Alex Susu via llvm-dev" <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>>

Hello. Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have to say that the definition of the "multiclass avx512_gather" from lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it. I currently have some serious problems with TableGen - it gives an assertion failure:

Hello. I fixed the bug reported in the previous post on this thread (<<llvm::MemSDNode::MemSDNode(unsigned int, unsigned int, const llvm::DebugLoc&, llvm::SDVTList, llvm::EVT, llvm::MachineMemOperand*): Assertion `memvt.getStoreSize() <= MMO->getSize() && "Size mismatch!"' failed.>>) The problem with this strange error reported comes from

Hi, I'm lowering some of the logical operators (by example the | operator) on integer32. Sadly my target only provide native instruction on high and low parts of 32 bits registers. So, I have to generate a sequence of two native instructions (LOR followed by HOR). I've introduced an Pseudo instruction with a custom inserter. def OR_A_oo : CLPPseudoInst<(ins

Hello. I wanted to inform that I fixed the bug from the previous email. The main reason for the bug was that I thought that the SDNode masked_gather is returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult to follow, error: "Assertion `New->getNumTypes() == 1"). masked_gather returns 2 values because: // SDTypeProfile -

...a recognized feature for this target (ignoring feature) '-3dnowa' is not a recognized feature for this target (ignoring feature) '-pclmul' is not a recognized feature for this target (ignoring feature) ..... The processor I used is generic, def : Processor<"generic", NoItineraries, []>; I used lldb to trace the code and didn't find it ran into ::ToggleFeature() or SubtargetFeatures::getFeatureBits() from where I see the warning string comes. Any guide or suggestion is appreciated! Thanks in advanced! -ye -------------- next part -------------- An HTML attachment...

Hi Alex, On 5 December 2016 at 18:00, Alex Susu <alex.e.susu at gmail.com> wrote: > We can compile it. Note that this is the only compilable code w.r.t. > using i64 or i64imm (in the 2 lines above: "dag InOperandList", "list<dag> > Pattern"). Yeah, you actually want to use "imm": list<dag> Pattern = [(int_repeat_x_times imm:$imm)];

Hi Alex, So far, the code you've mentioned only defines a couple tablegen classes but doesn't define the instruction itself. To define the instruction you will also need a 'def' statement. For MIPS MSA, this statement looks like this: def LD_D: LD_D_ENC, LD_D_DESC; This defines an instruction (LD_D) with the encoding specified by the LD_D_ENC class, and the operation

Hello. Hal, the problem I have is that it doesn't advance at the next available instruction - it always gets the same store. This might be because I did not specify in a file like [Target]Schedule.td the functional units, processor and instruction itineraries. Regarding the Stalls argument to my method [Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the