search for: newval

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2014 May 29
3
[LLVMdev] Proposal: "load linked" and "store conditional" atomic instructions
...A weak cmpxchg would go a long way to resolving this, but it's still difficult to see a path from an IR-level "cmpxchg weak" to optimal "atomicrmw lambda" support in LL/SC backends. Given C like void atomic_foo(int *addr) { int oldval = *addr; do { newval = foo(oldval); } while (__c11_compare_exchange_weak(addr, &oldval, newval)); The cmpxchg representation would be something like: define void @atomic_foo(int *addr) { entry: %firstval = load i32* %addr br label %loop loop: %oldval = phi i32 [%firstval,...
2015 Apr 24
3
[LLVMdev] Floating point atomic load and add
Quoting Tim Northover <t.p.northover at gmail.com>: > On 24 April 2015 at 13:53, Tyler Denniston <tyler at csail.mit.edu> wrote: >> I'm wondering how I can create an atomic load and add instruction for >> floating point values. If I use IRBuilder::CreateAtomicRMW() I get the >> error message: "atomicrmw operand must have integer type". > >
2003 Dec 14
1
compile error with C code and standalone R math C library
....c ********************************************************************** #include <stdio.h> #include <assert.h> #define T 3 #define INITVAL 1 #define MATHLIB_STANDALONE #define THETA 2 #include <Rmath.h> #include <time.h> void advance(double *node, int *current_pos, double newval); void retreat(double *node, int *current_pos); double new_val(double *node, double theta, int current_pos); double accept_prob(double *node, double theta, int current_pos); double accept_prob_fn(double a, double y); int main() { int currentpos = 0; int i; double newval, node[T+2], theta =...
2008 Oct 14
3
Server settings for BackgrounDRB?
I have backgroundrb working locally and everything''s fine. However, i can''t get it running on our server. I read a blog post by David Burger about backgroundrb (http://david-burger.blogspot.com/2008/04/backgroundrb-rails-notes.html#comment-form) and it says that you set up your backgroundrb.yml file with a different section for each environment you want to use. Mine looks like
2008 Jun 30
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...I'd prefer to fix the lowering if possible; the pseudo instructions are only used in three places, so it shouldn't be a huge change. I need to generate labels in PPCTargetLowering::LowerAtomicCMP_SWAP however: how do I do that? FWIW the code it needs to emit is: ; inputs: ptr, oldval, newval loop: lwarx $tmp, 0, $ptr cmpw $oldval, $tmp bne- exit stwcx. $newval, 0, $ptr bne- loop exit: ... Cheers, Gary -- http://gbenson.net/
2014 May 29
4
[LLVMdev] Proposal: "load linked" and "store conditional" atomic instructions
...rlier. For example the return value of the C++11 and C11 compare_exchange operations is actually whether the exchange succeeded, which leads to some common idioms in Clang-produced IR. >From "if(__c11_compare_exchange_strong(...))": %loaded = cmpxchg i32* %addr, i32 %oldval, i32 %newval seq_cst seq_cst %success = icmp eq i32 %loaded, %oldval br i1 %success, label %true, label %false the control-flow here should be something like: loop: %loaded = load linked i32* %addr seq_cst %trystore = icmp eq %loaded, %oldval br i1 %trystore, label %store.cond, lab...
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...her); SDOperand Ops[] = { - Chain, // Chain - Ptr, // Ptr - Label, // Label + Chain, + Ptr, + Incr, }; - SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3); - Chain = Load.getValue(1); - - // Compute new value. - SDOperand NewVal = DAG.getNode(ISD::ADD, VT, Load, Incr); - - // Issue a "store and check". - SDOperand Ops2[] = { - Chain, // Chain - NewVal, // Value - Ptr, // Ptr - Label, // Label - }; - SDOperand Store = DAG.getNode(PPCISD::STC...
2008 Jun 30
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...the lowering if possible; the pseudo instructions > are only used in three places, so it shouldn't be a huge change. > I need to generate labels in PPCTargetLowering::LowerAtomicCMP_SWAP > however: how do I do that? FWIW the code it needs to emit is: > > ; inputs: ptr, oldval, newval > loop: > lwarx $tmp, 0, $ptr > cmpw $oldval, $tmp > bne- exit > stwcx. $newval, 0, $ptr > bne- loop > exit: > ... > > > Cheers, > Gary > > -- > http://gbenson.net/ > _______________________________________...
2008 Jul 08
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >
2008 Jul 11
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...her); SDOperand Ops[] = { - Chain, // Chain - Ptr, // Ptr - Label, // Label + Chain, + Ptr, + Incr, }; - SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3); - Chain = Load.getValue(1); - - // Compute new value. - SDOperand NewVal = DAG.getNode(ISD::ADD, VT, Load, Incr); - - // Issue a "store and check". - SDOperand Ops2[] = { - Chain, // Chain - NewVal, // Value - Ptr, // Ptr - Label, // Label - }; - SDOperand Store = DAG.getNode(PPCISD::STC...
2008 Jul 11
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36
2012 Dec 28
1
[LLVMdev] [PATCH] LLVM build failure on OpenBSD/mips64
...n" ".set reorder\n" @@ -168,9 +168,9 @@ // Rewrite the function stub so that we don't end up here every time we // execute the call. We're replacing the first four instructions of the // stub with code that jumps to the compiled function: - // lui $t9, %hi(NewVal) - // addiu $t9, $t9, %lo(NewVal) - // jr $t9 + // lui $25, %hi(NewVal) + // addiu $25, $25, %lo(NewVal) + // jr $25 // nop int Hi = ((unsigned)NewVal & 0xffff0000) >> 16;
2008 Jul 10
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:
2015 Apr 24
2
[LLVMdev] Floating point atomic load and add
> } while (__c11_atomic_compare_exchange_weak( > addr, &oldval, newval, memory_order_seq_cst, memory_order_relaxed)); Actually, I think this condition is inverted. Should be "while (!_c11...". Sorry about that. Tim.
2008 Jul 09
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...her); SDOperand Ops[] = { - Chain, // Chain - Ptr, // Ptr - Label, // Label + Chain, + Ptr, + Incr, }; - SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3); - Chain = Load.getValue(1); - - // Compute new value. - SDOperand NewVal = DAG.getNode(ISD::ADD, VT, Load, Incr); - - // Issue a "store and check". - SDOperand Ops2[] = { - Chain, // Chain - NewVal, // Value - Ptr, // Ptr - Label, // Label - }; - SDOperand Store = DAG.getNode(PPCISD::STC...
2008 Jul 08
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:
2008 Jul 02
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...her); SDOperand Ops[] = { - Chain, // Chain - Ptr, // Ptr - Label, // Label + Chain, + Ptr, + Incr, }; - SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3); - Chain = Load.getValue(1); - - // Compute new value. - SDOperand NewVal = DAG.getNode(ISD::ADD, VT, Load, Incr); - - // Issue a "store and check". - SDOperand Ops2[] = { - Chain, // Chain - NewVal, // Value - Ptr, // Ptr - Label, // Label - }; - SDOperand Store = DAG.getNode(PPCISD::STC...
2010 Oct 05
1
binary tree construction in R
Hi all, I'm very new to R and I'm trying to construct a threaded binary tree using recursive functions. I'm very confused was wondering if anyone had any R sample code they would share. I've come across a lot of C++ code(nothing in R) and this is not helping. best, MK -- View this message in context:
2007 Oct 21
2
image 256 x 920 data points too slow
Dear R gurus, I'm trying to visualize a matrix 256 x 920 using image(), but i find the display too slow (~ 1 minute ?? admittedly, my iBook G4 isn't very fast). The aim is not to get a good resolution image, but rather have a quick look at the matrix. I couldn't find a way to plot a smaller set of points from my data in a sensible manner (basically, i want to decrease the