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On Tue, Mar 17, 2015 at 6:14 PM, Tim Northover <t.p.northover at gmail.com> wrote: >> As a simplification, the compiler deals almost exclusively in pseudo >> instructions. By x86 analogy, using pseudos to unfold a TEST32rm into >> MOV32rm + TEST32rr means I can skip the complex operand fitting effort >> needed to pick specific machine instructions. There are many

  Hi Aries. Thanks very much! Precisely this is the situation! There're two consecutive branches (br1cond and br2uncond). Inside of AnalyzeBranch, there's an opcode swap of br2uncond (ex. j_foward to j_backward). There I do BuildMI (newOpcode) and followed by br2uncond->eraseFromParent(). This results in br1cond loosing it's label/offset. How could I resolve this? Best regards, Girish. May be you have branched to a BB which has been deleted. > > >On 24 January 2012 20:16, girish gulawani <girishvg at yahoo.com> w...

...hanging opcode > > Is there a simple way to just change the opcode of a machine > instruction. > > I have a lot of long/short pairs where when I know the offset, i can > replace the long version with the short version. Are you looking for something like this: MI.setDesc(TII.get(NewOpcode)); This is in PPCRegisterInfo::eliminateFrameIndex. -Hal > > Tia. > > REed > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmde...

Is there a simple way to just change the opcode of a machine instruction. I have a lot of long/short pairs where when I know the offset, i can replace the long version with the short version. Tia. REed

...39; can never be matched!"); // FIXME: Should reject these. The ARM backend hits this with $lane in a // bunch of instructions. It is unclear what the right answer is. … Is there a way to fix this limitation? I would like to express: InstAlias<(opcode $rd, $rd, $rs1), (newopcode $rd, $rs1)> Thank you, Ana. -- Ana Pazos Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.

> Precisely this is the situation! There're two consecutive branches (br1cond > and br2uncond). Inside of AnalyzeBranch, there's an opcode swap of br2uncond > (ex. j_foward to j_backward). There I do BuildMI (newOpcode) and followed by > br2uncond->eraseFromParent(). This results in br1cond loosing it's > label/offset. How could I resolve this? Your code is broken. AnalyzeBranch should not modify anything. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersbu...

...ot;); > // FIXME: Should reject these. The ARM backend hits this with $lane in a > // bunch of instructions. It is unclear what the right answer is. > … > > Is there a way to fix this limitation? > > I would like to express: InstAlias<(opcode $rd, $rd, $rs1), (newopcode $rd, $rs1)> > > Thank you, > Ana. > > > -- > Ana Pazos > Qualcomm Innovation Center, Inc. > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project. > _______________________________________________ > L...

Hello All. On a particular target the back-end generates an instruction like: beqz      r2, "$BB0_-1"   Is it a back-end specific issue? Could someone please help me figure out how this gets resolved? What confuses me is, all other branches are correctly labelled and resolved!  Thanks. Girish. -------------- next part -------------- An HTML attachment was scrubbed... URL:

May be you have branched to a BB which has been deleted. On 24 January 2012 20:16, girish gulawani <girishvg at yahoo.com> wrote: > > Hello All. > On a particular target the back-end generates an instruction like: > beqz r2, "$BB0_-1" > > Is it a back-end specific issue? Could someone please help me figure out > how this gets resolved? What confuses me

Hello Anton. Thanks for the comment. > Precisely this is the situation! There're two consecutive branches (br1cond >> and br2uncond). Inside of AnalyzeBranch, there's an opcode swap of br2uncond >> (ex. j_foward to j_backward). There I do BuildMI (newOpcode) and followed by >> br2uncond->eraseFromParent(). This results in br1cond loosing it's >> label/offset. How could I resolve this? >Your code is broken. AnalyzeBranch should not modify anything. > > > >I was taking a clue from Mips/MipsInstrInfo.cpp: AnalyzeBranch :...

...e. The ARM backend hits this with >> $lane in a >> // bunch of instructions. It is unclear what the right answer >> is. >> … >> >> Is there a way to fix this limitation? >> >> I would like to express: InstAlias<(opcode $rd, $rd, $rs1), (newopcode >> $rd, $rs1)> >> >> Thank you, >> Ana. >> >> >> -- >> Ana Pazos >> Qualcomm Innovation Center, Inc. >> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, >> a Linux Foundation Collaborative Project. >> _...

...SDep::Kind DepType, MachineBasicBlock::iterator&MII, >> + const TargetRegisterClass* RC) { >> + >> + assert (DepType == SDep::Data); >> + const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; >> + >> + int NewOpcode; >> + if (RC == Hexagon::PredRegsRegisterClass) >> + NewOpcode = GetDotNewPredOp(MI->getOpcode()); >> + else >> + NewOpcode = GetDotNewOp(MI->getOpcode()); >> + MI->setDesc(QII->get(NewOpcode)); >> + >> + return true; >> +} >&...