search for: new_regs

From: Rodrigo Vivi <rodrigo.vivi at gmail.com> These are missed cases that I just identified with allyesconfig build. Fixes: 2966141ad2dd ("drm/ttm: rename ttm_mem_reg to ttm_resource.") Cc: Dave Airlie <airlied at redhat.com> Cc: Ben Skeggs <bskeggs at redhat.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com> --- drivers/gpu/drm/nouveau/nouveau_bo.h

On Fri, 7 Aug 2020 at 11:13, Rodrigo Vivi <rodrigo.vivi at intel.com> wrote: > > From: Rodrigo Vivi <rodrigo.vivi at gmail.com> > > These are missed cases that I just identified with allyesconfig build. > Is this against drm-tip? it's a merge problem, that I thought I'd already addressed, but tip seems to have lost it. Dave. > Fixes: 2966141ad2dd

> So what addIntervalsToSpills returns are new intervals to allocate with > infinite weights, right? > And I need not to allocate the old interval. Should hasStackSlot return true > on its register then? > I am not very sure about addIntervalsToSpill, but, for all the registers created to replace a spilled registers, they must have a stack slot assigned to them. I am sending you my

So what addIntervalsToSpills returns are new intervals to allocate with infinite weights, right? And I need not to allocate the old interval. Should hasStackSlot return true on its register then? On 8/21/06, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > Well, someone correct me if am wrong, but, you still have to allocate > physical registers to them,

I made the change to the BuildMI() call. Again, I don't think that matters. #define BUILD_INS(opcode, new_reg, i) \ BuildMI(*MBB, OldMI, MBBI->getDebugLoc(), TII->get(X86::opcode)) \ .addReg(X86::new_reg, kill).addImm(i) I didn't completely understand your other proposed change: ​ for (MachineBasicBlock::iterator MBBI = MBB->begin();

This seems a very natural approach but I probably am having a trouble with the iterator invalidation. However, looking at other peephole optimizers passes, I couldn't see how to do this: #define BUILD_INS(opcode, new_reg, i) \ BuildMI(*MBB, MBBI, MBBI->getDebugLoc(), TII->get(X86::opcode)) \ .addReg(X86::new_reg, kill).addImm(i) for

I'm writing a peephole pass and I'm done with the X86_64 instruction level detail work. But I'm having difficulty with the basic block surgery of replacing the old MachineInst. The peephole pass gets called per MachineFunction and then iterates over each MachineBasicBlock and in turn over each MachineInst. When it finds an instruction which should be replaced, it builds a new

I'm not sure about one thing: you assign stack slot to each new register you replace the spilled one with. And then you need to allocate physical registers to them. Is it possible to assign physical register to the virtual one which has a stack slot already? On 8/21/06, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > > So what addIntervalsToSpills

Purely conjecture, but I think the original locking inversion with the legacy page flip code between flipping and ttm's bo move function shoudn't exist anymore with atomic: With atomic the bo pinning and actual modeset commit is completely separated in the code patsh. This annotation was originally added in commit 060810d7abaabcab282e062c595871d661561400 Author: Ben Skeggs <bskeggs at

On Aug 6, 2012, at 11:00 AM, Vincent Lejeune <vljn at ovi.com> wrote: > Ok. > > I tried to do it using a pass after register allocation, lowering NEG/ABS instructions. > However I met a problem : apparently getNextOperandForReg() can returns a MachineOperand before the one I'm processing. > > The following code snippet : > > > void

The page_count variable in nv04_bo_move_m2mf was redundantly initialized twice with the same value. Signed-off-by: Sergi Granell <xerpi.g.12 at gmail.com> --- drivers/gpu/drm/nouveau/nouveau_bo.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 548f36d3..2724907a 100644 ---

Hello. I am making a backend for a virtual machine. But it does assume infinite number of virtual registers unlike those of usual machines. In this case, how can I implement this? Would you mind telling me some tips? Thank you so much. Seung Jae Lee

Ben, did you have a chance to look at this? -Daniel On Mon, Aug 3, 2020 at 1:22 PM Maarten Lankhorst <maarten.lankhorst at linux.intel.com> wrote: > > Op 02-08-2020 om 20:18 schreef Daniel Vetter: > > Purely conjecture, but I think the original locking inversion with the > > legacy page flip code between flipping and ttm's bo move function > > shoudn't exist

There are 11 BuildMI() functions in MachineInstrBuilder.h including four using the iterator and one using an instruction. But I just don't think that's it. The creation of the new instruction works fine (works fine with OldMI as well) and the new instruction is present in the assembly output. The problem is removing the old instruction correctly. > The loop header needs to be

Do you know any backend that implement instructions as a flag modifier in instruction ? Thank, Vincent Lejeune ----- Mail original ----- > De : Jakob Stoklund Olesen <stoklund at 2pi.dk> > À : Vincent Lejeune <vljn at ovi.com> > Cc : "llvmdev at cs.uiuc.edu (LLVMdev at cs.uiuc.edu)" <llvmdev at cs.uiuc.edu> > Envoyé le : Lundi 6 août 2012 20h06 >

On Wed, 30 Sep 2020 at 00:52, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > On Thu, Sep 17, 2020 at 3:15 PM Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > > > Ben, did you have a chance to look at this? > > Ping > -Daniel > > > On Mon, Aug 3, 2020 at 1:22 PM Maarten Lankhorst > > <maarten.lankhorst at linux.intel.com> wrote:

Hi, R600 hardware (Radeon gfx card) does neither have a NEG nor an ABS instruction ; however any sources operand can be negated/abs'd by setting a bit for every source operand in the final bytecode (but not DST). A good way of modeling this behavior in LLVM is by using TargetFlag on operand. Currently the R600 LLVM backend in Mesa lower NEG and ABS DAG instruction to a MOV + TargetFlag using

On 2/18/20 1:44 PM, Christian K?nig wrote: > Am 18.02.20 um 13:40 schrieb Thomas Zimmermann: >> Hi >> >> Am 17.02.20 um 16:04 schrieb Nirmoy Das: >>> GPU address handling is device specific and should be handle by its >>> device >>> driver. >>> >>> Signed-off-by: Nirmoy Das <nirmoy.das at amd.com> >>> ---

On Wed, 30 Sep 2020 at 19:37, Daniel Vetter <daniel at ffwll.ch> wrote: > > On Wed, Sep 30, 2020 at 10:45:05AM +1000, Ben Skeggs wrote: > > On Wed, 30 Sep 2020 at 00:52, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > > > > > On Thu, Sep 17, 2020 at 3:15 PM Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > > > > > > >

Am 18.02.20 um 19:16 schrieb Thomas Zimmermann: > Hi > > Am 18.02.20 um 18:13 schrieb Nirmoy: >> On 2/18/20 1:44 PM, Christian K?nig wrote: >>> Am 18.02.20 um 13:40 schrieb Thomas Zimmermann: >>>> Hi >>>> >>>> Am 17.02.20 um 16:04 schrieb Nirmoy Das: >>>>> GPU address handling is device specific and should be handle by its