search for: netburst

Just a thought If the I386 (or i686, never could figure out why the name change) disk doesn't quite fit on the DVD+, and needs a DVD-, this might put some folks at an inconvenience. I wonder if the difference between fitting and not fitting is small enough, so that some amount of pruning might make it fit on the DVD+R image. Some ways to prune could be: a) Create two versions of the

...were previously modified by other instructions. For example, partial register stalls occurs with a read to AX while previous instructions stored AL and AH, or a read to EAX while previous in struction modified AX. The delay of a partial register stall is small in processors based on Intel Core and NetBurst microarchitectures, and in Pentium M processor (with CPUID signature family 6, model 13), Intel Core Solo, and Intel Core Duo processors. Pentium M processors (CPUID signature with family 6, model 9) and the P6 family incur a large penalty. <<Enq quote>> So for compact code, yes, it...

...uctions. For example, > partial register > stalls occurs with a read to AX while previous instructions stored AL > and AH, or a read > to EAX while previous in > struction modified AX. > The delay of a partial register stall is small in processors based on > Intel Core and > NetBurst microarchitectures, and in Pentium M processor (with CPUID > signature > family 6, model 13), Intel Core Solo, > and Intel Core Duo processors. Pentium M > processors (CPUID signature with family 6, > model 9) and the P6 family incur a large > penalty. > <<Enq quote>&g...

...y? A locked cmpxchg ends up being anything between ~15-50 cycles depending on microarchitecture if things are already exclusively in the cache (with the P4 being an outlier, and all locked instructions tend to take ~100+ cycles, but I can't say I can really find it in myself to even care about netburst any more). The most noticeable downside we've seen has been when we've used "read-op-cmpxchg" as a _replacement_ for something like "lock [x]add", when that "read+cmpxchg" has caused two cacheline ops (cacheline first loaded shared by the read, then exclusive...

...y? A locked cmpxchg ends up being anything between ~15-50 cycles depending on microarchitecture if things are already exclusively in the cache (with the P4 being an outlier, and all locked instructions tend to take ~100+ cycles, but I can't say I can really find it in myself to even care about netburst any more). The most noticeable downside we've seen has been when we've used "read-op-cmpxchg" as a _replacement_ for something like "lock [x]add", when that "read+cmpxchg" has caused two cacheline ops (cacheline first loaded shared by the read, then exclusive...

...artial register >> stalls occurs with a read to AX while previous instructions stored AL >> and AH, or a read >> to EAX while previous in >> struction modified AX. >> The delay of a partial register stall is small in processors based on >> Intel Core and >> NetBurst microarchitectures, and in Pentium M processor (with CPUID >> signature >> family 6, model 13), Intel Core Solo, >> and Intel Core Duo processors. Pentium M >> processors (CPUID signature with family 6, >> model 9) and the P6 family incur a large >> penalty. >...

...stalls occurs with a read to AX while previous instructions stored AL >>> and AH, or a read >>> to EAX while previous in >>> struction modified AX. >>> The delay of a partial register stall is small in processors based on >>> Intel Core and >>> NetBurst microarchitectures, and in Pentium M processor (with CPUID >>> signature >>> family 6, model 13), Intel Core Solo, >>> and Intel Core Duo processors. Pentium M >>> processors (CPUID signature with family 6, >>> model 9) and the P6 family incur a large &g...

...ad to AX while previous instructions stored AL >>>> and AH, or a read >>>> to EAX while previous in >>>> struction modified AX. >>>> The delay of a partial register stall is small in processors based on >>>> Intel Core and >>>> NetBurst microarchitectures, and in Pentium M processor (with CPUID >>>> signature >>>> family 6, model 13), Intel Core Solo, >>>> and Intel Core Duo processors. Pentium M >>>> processors (CPUID signature with family 6, >>>> model 9) and the P6 fam...

( I don't know if it's allowed to ask such question, if not, please remind me. ) I know Intel implemented several static branch prediction mechanisms these years: * 80486 age: Always-not-take * Pentium4 age: Backwards Taken/Forwards Not-Taken * PM, Core2: Didn't use static prediction, randomly depending on what happens to be in corresponding BTB entry , according to agner's

Try using x86 mode rather than Intel64 mode. I have definitely gotten it to use both ah and al in 32 bit x86 code generation. In particular, I have seen that in loops for both the spec2000 and spec2006 versions of bzip. It can happen, but it does only rarely. Kevin Smith >-----Original Message----- >From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of >Krzysztof

Greetings LLVM Developers, My name is Kazuo, I’m the head of the largest Silicon Graphics IRIX community on the internet. I’m approaching this mailing list to see if any MIPS developers who hang out here are interested in developing the LLVM/Clang Compiler system for IRIX. There’s a growing need as GCC removed support for us from 4.8, over six years ago and since then we’ve absolutely languished

...supports 4 MCE banks CPU0: Thermal monitoring enabled (TM1) SMP alternatives: switching to UP code ACPI: Core revision 20090903 Enabling APIC mode: Flat. Using 1 I/O APICs ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 CPU0: Intel(R) Pentium(R) 4 CPU 1.50GHz stepping 02 Performance Events: Netburst events, Netburst P4/Xeon PMU driver. ... version: 0 ... bit width: 40 ... generic registers: 18 ... value mask: 000000ffffffffff ... max period: 0000007fffffffff ... fixed-purpose events: 0 ... event mask: 000000000003ffff NMI w...

I'm trying to see how the x86 backend deals with the relationship between AL, AH and AX, but I can't get it to generate any code that would expose an interesting scenario. For example, I wrote this piece: typedef struct { char x, y; } struct_t; struct_t z; struct_t foo(char *p) { struct_t s; s.x = *p++; s.y = *p; z = s; s.x++; return s; } But the output at -O2

In virtualized environment there are mainly three problems related to spinlocks that affect performance. 1. LHP (lock holder preemption) 2. Lock Waiter Preemption (LWP) 3. Starvation/fairness Though ticketlocks solve the fairness problem, it worsens LWP, LHP problems. pv-ticketlocks tried to address this. But we can further improve at the cost of relaxed fairness. In this patch, we form a batch

In virtualized environment there are mainly three problems related to spinlocks that affect performance. 1. LHP (lock holder preemption) 2. Lock Waiter Preemption (LWP) 3. Starvation/fairness Though ticketlocks solve the fairness problem, it worsens LWP, LHP problems. pv-ticketlocks tried to address this. But we can further improve at the cost of relaxed fairness. In this patch, we form a batch

Greetings, I got the below dmesg and the first bad commit is commit cf39c8e5352b4fb9efedfe7e9acb566a85ed847c Merge: 3398d25 23b7eaf Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Wed Sep 4 17:45:39 2013 -0700 Merge tag ''stable/for-linus-3.12-rc0-tag'' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip Pull Xen updates from Konrad

The options -x -v gave me an error that no such option so I ruined it with —debug option. root@ny2proxd03:/var/lib/vz/images/100# virt-resize --expand /dev/sda3 vm-100-disk-1.qcow2 vm-100-disk-1.qcow2.resized --debug command line: virt-resize --expand /dev/sda3 vm-100-disk-1.qcow2 vm-100-disk-1.qcow2.resized --debug Examining vm-100-disk-1.qcow2 ... libguestfs: trace: add_drive

...to 0f 1f 44 00 00 [ 0.209022] ftrace: allocating 22317 entries in 88 pages [ 0.217996] APIC routing finalized to flat. [ 0.231367] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 [ 0.233977] CPU0: Intel Common KVM processor stepping 01 [ 0.340411] Performance Events: unsupported Netburst CPU model 6 no PMU driver, software events only. [ 0.346425] NMI watchdog disabled (cpu0): hardware events not enabled [ 0.348011] Brought up 1 CPUs [ 0.348962] Total of 1 processors activated (4788.00 BogoMIPS). [ 0.355912] devtmpfs: initialized [ 0.359025] regulator: core version 0...