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...unit test side. Anyway I tried to push https://reviews.llvm.org/D48850 <https://reviews.llvm.org/D48850> in order to extend llc to be more amenable in the situations we want to test, but it ultimately wasn't accepted. > > - Matthias > >> On Jul 2, 2018, at 2:35 PM, Aditya Nandakumar via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> When writing MachineFunction unit tests, I find it quite tedious to verify correctness in C++. I would like to use FileCheck in UnitTests because FileCheck is extremely convenient/rob...

...Engineer Compilation Tools ARM > -----Original Message----- > From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of > Renato Golin via llvm-dev > Sent: Thursday, March 30, 2017 9:54 AM > To: Quentin Colombet > Cc: llvm-dev; Justin Bogner; Ahmed Bougacha; Aditya Nandakumar > Subject: Re: [llvm-dev] [GlobalISel][AArch64] Toward flipping the switch for > O0: Please give it a try! > > On 30 March 2017 at 00:27, Quentin Colombet <qcolombet at apple.com> > wrote: > > On iOS we are at 100% pass rate in 00 g for the LLVM test suite, > > sta...

When writing MachineFunction unit tests, I find it quite tedious to verify correctness in C++. I would like to use FileCheck in UnitTests because FileCheck is extremely convenient/robust to verify correctness. In order to do so, I moved most of FileCheck’s implementation into a header (Support/FileCheck.h) and updated FileCheck.cpp to use this. I ran into this while writing some target agnostic

...to DAGIsel in case of failure. You can use -global-isel-abort=2 option. llc -global-isel -pass-remarks-missed="gisel-*" -global-isel-abort=2 simple_foo.ll Regards, Igor From: S. Bharadwaj Yadavalli [mailto:bharadwajy at gmail.com] Sent: Thursday, November 09, 2017 03:36 To: Aditya Nandakumar <proaditya at gmail.com> Cc: Craig Topper <craig.topper at gmail.com>; llvm-dev <llvm-dev at lists.llvm.org>; Breger, Igor <igor.breger at intel.com> Subject: Re: [llvm-dev] [GlobalISel] [X86] unable to legalize instruction Sorry for the late follow-up. Here is the output...

On 11/11/2017 12:44 PM, Amara Emerson wrote: > >> On Nov 10, 2017, at 10:04 PM, Aditya Nandakumar <proaditya at gmail.com >> <mailto:proaditya at gmail.com>> wrote: >>> >>> The current DAGCombine, being constructed on top of SDAG, has a kind >>> of built-in CSE and automatic DCE. How will things change, if >>> they'll change, in this...

I believe if you pass(iirc) -pass-remarks-missed=“gisel-*”, it’ll print the instruction it failed to legalize. Sent from my iPhone > On Oct 11, 2017, at 6:44 PM, S. Bharadwaj Yadavalli via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Thanks for your quick reply. > > Here its is: > > =========== > > ; ModuleID = 'simple_foo.c' > source_filename

> On Nov 11, 2017, at 11:03 AM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > On 11/11/2017 12:44 PM, Amara Emerson wrote: >> >>> On Nov 10, 2017, at 10:04 PM, Aditya Nandakumar <proaditya at gmail.com <mailto:proaditya at gmail.com>> wrote: >>>> >>>> The current DAGCombine, being constructed on top of SDAG, has a kind of built-in CSE and automatic DCE. How will things change, if they'll change, in this new model? >>> Hi Ha...

Hi I am new to the LLVM infrastructure. I would like to contribute to the project. Looking at all the information available on LLVM, I am a little overwhelmed. I have taken a compiler design course and have worked on another compiler project. I was wondering if anyone could suggest a little roadmap where I can get my feet wet a little. I am currently not sure where to start. I know this is not

Hi LLVM developers, Thank Daniel Sanders, Aditya Nandakumar and Justin Bogner's Tutorial[1]: Head First into GlobalISel about how to port, and Aditya took BPF target as a simple instance: bool BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,                                   const Value *Val, unsigned VReg) const {   assert(!Val == !...

> On Nov 10, 2017, at 10:19 AM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > On 11/10/2017 11:12 AM, Amara Emerson via llvm-dev wrote: >> Hi everyone, >> >> This RFC concerns the design and architecture of a generic machine instruction combiner/optimizer framework to be developed as part of the GISel pipeline. As we transition from

...;mailto:qcolombet at apple.com> [mailto:qcolombet at apple.com <mailto:qcolombet at apple.com>] > Sent: 14 November 2017 23:11 > To: Quentin Colombet > Cc: Oliver Stannard; llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>; Justin Bogner; Ahmed Bougacha; Aditya Nandakumar; nd > Subject: Re: [llvm-dev] [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! > > To give an update here, we actually are not missing a mapping. The code complains because we are copying around a fp16 into a gpr32 and that shouldn’t be done with a copy (def...

...t;> >> From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org <mailto:llvm-dev-bounces at lists.llvm.org>] On Behalf Of Quentin Colombet via llvm-dev >> Sent: 13 November 2017 18:27 >> To: Kristof Beyls >> Cc: llvm-dev; nd; Ahmed Bougacha; Justin Bogner; Aditya Nandakumar >> Subject: Re: [llvm-dev] [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! >> >> Hi Kristof, >> >> >> On Nov 13, 2017, at 9:10 AM, Kristof Beyls <Kristof.Beyls at arm.com <mailto:Kristof.Beyls at arm.com>> wrote: &...

...;mailto:qcolombet at apple.com> [mailto:qcolombet at apple.com <mailto:qcolombet at apple.com>] > Sent: 14 November 2017 23:11 > To: Quentin Colombet > Cc: Oliver Stannard; llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>; Justin Bogner; Ahmed Bougacha; Aditya Nandakumar; nd > Subject: Re: [llvm-dev] [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! > > To give an update here, we actually are not missing a mapping. The code complains because we are copying around a fp16 into a gpr32 and that shouldn’t be done with a copy (def...

...c msg: /tmp/test-e06964.sh clang-6.0: note: diagnostic msg: ******************** Oliver From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Quentin Colombet via llvm-dev Sent: 13 November 2017 18:27 To: Kristof Beyls Cc: llvm-dev; nd; Ahmed Bougacha; Justin Bogner; Aditya Nandakumar Subject: Re: [llvm-dev] [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try! Hi Kristof, On Nov 13, 2017, at 9:10 AM, Kristof Beyls <Kristof.Beyls at arm.com<mailto:Kristof.Beyls at arm.com>> wrote: Hi Quentin, My only remaining concern is around ABI compa...

Hi all, I'm trying to get GlobalISel up and running on an off-tree architecture and am thinking I must be doing something wrong, given by how few things actually work. Namely, any ImmLeaf pattern will fail to match if there is a (TRUNC/ZEXT/SEXT) applied to the constant operand, all of which are commonly created through Legalization. This is due to G_CONSTANT being explicitly looked for by

Hi, GlobalISel, the SelectionDAG replacement, has come a long way since initially discussed on the mailing list and its last discussion at the EuroLLVM BoF (https://etherpad.net/p/GlobalISel <https://etherpad.net/p/GlobalISel>). We believe we are close to the point of enabling it by default on AArch64 at O0. We now would like to enlist your help to get there. *** Quick Status *** On iOS

Thanks for your quick reply. Here its is: =========== ; ModuleID = 'simple_foo.c' source_filename = "simple_foo.c" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.13.0" ; Function Attrs: noinline nounwind optnone ssp uwtable define i32 @foo(i32 %a, i32 %b, i32 %c) #0 { entry: %retval = alloca i32, align

> On May 5, 2020, at 2:45 PM, Ties Stuij <Ties.Stuij at arm.com> wrote: > > Quentin: Thanks for the info. I was under the impression that the LLVM community at large would prefer to extend the IR type to a bfloat MVT type. I've made a number of patches to implement this up to a point for AArch64. I can post those on Phab and start a thread to sample opinions. Sounds good to

Hi Quentin, My only remaining concern is around ABI compatibility. The following commit seems to indicate that in the previous round of evaluation, we didn’t find an existing ABI compatibility issue: http://llvm.org/viewvc/llvm-project?view=revision&revision=311388. I haven’t looked into the details of this issue - so maybe I’m worried over nothing? I’m wondering if since then on your side

...ombine Rules using MIR syntax with a few bits glued on to interface with the algorithm and escape into C++ when we need to. Eventually, ISel rules may follow suit. Thanks to the following people for their help in playing with this syntax and discussing it with me over the last couple weeks: Aditya Nandakumar Adrian Prantl Ahmed Bougacha Amara Emerson Jessica Paquette Michael Berg Justin Bogner Roman Tereshin Vedant Kumar Volkan Keles Their feedback has vastly improved this over the original version and it was through those discussions that the idea of re-using MIR as a declarative definition was born....