search for: n64

The ELF relocation record format is different for N64 which many Mips 64 ABIs use than for O64 which many if not all other target ABIs use. The question I have is whether to treat N64 as a valid generic variant or should it be treated as target specific? My contention is that it should be treated as an alternative generic format handled recognized...

Has anyone experimented with generating non-PIC for MIPS64 and the n64 ABI? Currently MipsISelLowering.cpp uses conditions like: if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) { } around any PIC code generation. Is generating non-PIC just untested, or is it known not to work? I can't find any discussion of it anywhere. I ran into this...

Actually, GCC will generate non-PIC for n64. Maybe that is a recent addition, but we are using its results. Even if PIC may be faster and smaller code, it seems that non-PIC is still useful for bare-metal. That's the driver of my interest. I guess we can just test what happens when that part of the conditional is removed. As a side...

On 24 June 2016 at 06:02, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote: > Hi, > > Having recently enabled IAS by default for the MIPS O32 ABI, I'm now trying to do the same thing for the MIPS N64 ABI. Unfortunately, it is not currently possible to enable IAS by default for the N64 ABI without also enabling it for the N32 ABI because this information is not reflected in the triple and that's the only information MipsMCAsmInfo has. What would it take to pass more information to MipsMCAsm...

Hi, Having recently enabled IAS by default for the MIPS O32 ABI, I'm now trying to do the same thing for the MIPS N64 ABI. Unfortunately, it is not currently possible to enable IAS by default for the N64 ABI without also enabling it for the N32 ABI because this information is not reflected in the triple and that's the only information MipsMCAsmInfo has. This would be fine if it N32 was also in a good state but...

...o IRObjectFile? The second problem is that IRLinker will link incompatible IR together because it doesn't know the ABI's involved in the link. It thinks it's sufficient to check that the triples are the same. How would you prevent it from linking IR intended for O32 with IR intended for N64? I'm also worried about the risk of undiscovered problems on the pass-MCTargetOptions-everywhere path but it's difficult to discuss those for obvious reasons. However, I think it's safe to say that there could be some major problems waiting to be discovered given that we don't have...

Has anyone managed to rn this? If yes, with what configuration on what distro and with which rom? Please help/ Help!

Thanks Renato and Rafael. > On 24 June 2016 at 06:02, Daniel Sanders <Daniel.Sanders at imgtec.com> > wrote: > > Hi, > > > > Having recently enabled IAS by default for the MIPS O32 ABI, I'm now > trying to do the same thing for the MIPS N64 ABI. Unfortunately, it is not > currently possible to enable IAS by default for the N64 ABI without also > enabling it for the N32 ABI because this information is not reflected in the > triple and that's the only information MipsMCAsmInfo has. > > What would it take to pass more...

But then I should write // CHECK: something // SSE: something // SSE3: something With this feature it can be write // {{[A-Z0-9]+}} : something From: James Y Knight [mailto:jyknight at google.com] Sent: Thursday, May 26, 2016 5:53 PM To: Ehsan Amiri <ehsanamiri at gmail.com> Cc: Elena Lepilkina <Elena.Lepilkina at synopsys.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject:

...aining issues as we discover them but we may fall back on reverting temporarily if too much breaks. We had to leave 64-bit MIPS targets using an external assembler for the moment since the integrated assembler has a number of issues with the N32 ABI which also prevents us making the switch for the N64 ABI because the relevant code cannot distinguish N32 from N64. Hopefully we'll be able to make the switch for those targets in the near future. Thanks to everyone who made this possible. Daniel Sanders Leading Software Design Engineer, MIPS Processor IP Imagination Technologies Limited http:/...

On Thu, May 26, 2016 at 10:35 AM, Ehsan Amiri via llvm-dev < llvm-dev at lists.llvm.org> wrote: > 7. Wildcard for prefixes - If some statements should be checked > regardless prefix, it should be used //{{*}}, //{{*}}-NEXT, //{{*}}-SAME > and etc. > >> 8. Prefix with regular expressions - If statement should be >> checked if prefix matches some regular

Hi, I'd like to experiment with the MIPS and PowerPC backends, but, considering that they aren't widely used processors, I'd like to start with the same environment (OS/ABI/linker) used by the people who work with these backends. So, what OS/ABI/linker use the people who use these backends for production work? Thanks!!

Hi all When I use user at ubuntu:/home$ clang -cc1 -triple mips64el-unknown-linux-gnu -ccc-clang-archs mips64el -mabi=n64 a.c I get a error: error: unknown argument: '-ccc-clang-archs' error: unknown argument: '-mabi=n64' So I use user at ubuntu:/home$ clang -ccc-host-triple mips64el-unknown-linux-gnu -mabi=n64 a.c I get s error like: clang: warning: unknown platform, assuming -mfloat-abi=soft In fi...

I'm cross-compiling for MIPS. The test-case is as simple as it can be: void foo() {} $clang -target mips64-octeon-linux -c -B path/to/cross/compiled/mips/assembler a.c And then I look at the object file: $ nm a.o 0000000000000020 t $tmp0 0000000000000000 T foo I would like to know what "$tmp0" is. Furthermore, if I pass -g to clang, I see a whole bunch of such symbols. Some of

Time to sell the N64 goods to make room for the next-gen! Please only respond to EMAIL as I will not be monitoring the news groups (: This is really an amazing system.. CDROM based.. If you can burn your ROM to a CD you can play directly from the station else you an upload through the parallel port.. This system wil...

...ries despite having a big-endian triple. The same applies to a lot of our code generation options. The most complicated one I'm aware of is mips-mti-linux-gnu which can produce code for nearly any Mips target when given the right options. The main issue I have at the moment is with the N32 and N64 ABI's. These are ILP32 and LP64 respectively, are mutually incompatible, and have traditionally used the same triple. There's an ARM example of the same problem at https://wiki.debian.org/Multiarch/Tuples#Why_not_use_GNU_triplets.3F. In that example, hard-float and soft-float both used arm-...

...Ses would be Linux/FreeBSD/NetBSD/OpenBSD. > > Endianness is somewhat variable as many MIPS designs have big endian and > little endian variants. Typically you can assume big endian but little > endian is > fairly common as well. > > For the ABI would be O32 for 32 bit MIPS and N64 for 64 bit MIPS. There is > another ABI, N32 which fulfils a similar role as X32 for x86_64 i.e. 32bit > pointers > with 64 integers. This is what stock GCC targets by default for mips64. > LLVM for > mips64 targets N64 by default for historical reasons. > > Historically, MIPS...

Hi, 3.5.1-rc1 has been tagged, so it is time to begin testing. We can always use more testers, so if you would like to volunteer, let me know. For those that are new to testing, please review the documentation for how validate a new release: http://llvm.org/docs/ReleaseProcess.html Remember that when we check for regressions we want to compare the test results of 3.5.1-rc1 with 3.5.0-final.

...nted a long time ago and I can only guess at this point but I'd say that there were some misinterpretations of the spec and given the popularity of GCC, the implementation became the new standard and it's something that LLVM needs to cope with. > There are a lot of MIPS ABIs. o32, n32, n64 - These came from the SGI world for IRIX originally, but were also adopted for linux and used in gcc for both. o64 - Invented at Cygnus for 64-bit processors eabi - Different one invented at Cygnus meabi - Invented with MIPS and Cygnus (and possibly others) in the late 90s as a new embedded abi. An...

...g Tan On Mon, Jun 16, 2014 at 5:30 PM, Matheus Almeida <Matheus.Almeida at imgtec.com> wrote: > Could you be more specific about what ABIs are you after ? The reason I'm asking is that there are several ABIs available for Mips and only a few of them are supported by LLVM (o32, n32 and n64). There are several ABIs defined by GNU with very little documentation that describes them (EABI is one example). > > We are aware that the available documentation and GCC disagree sometimes and given that GCC is the de-facto standard, LLVM tries to follow GCC's behaviour as close as poss...