search for: myinstr

Hi everyone, inline asm code is like below: void test(unsigned short a) { asm("myinstr my16bitreg, %0"::"r"(a)); } I want it generate instruction "myinstr my16bitreg, r15" I execute llc test.bc -march = msp430 -o test.s then it reports "LLVM ERROR: Couldn't allocate input reg for constraint 'r' !" What's the reaso...

Hello > inline asm code is like below: > > void test(unsigned short a) { >    asm("myinstr          my16bitreg, %0"::"r"(a)); > } > I want it generate instruction "myinstr          my16bitreg, r15" > > I execute > llc test.bc -march = msp430 -o test.s > then it reports > "LLVM ERROR: Couldn't allocate input reg for constraint 'r&...

Hi Anton, Need i write additial c/c++/td code for my target to support inline asm? Regrads 2009/12/18 Anton Korobeynikov <anton at korobeynikov.info> > Hello > > > inline asm code is like below: > > > > void test(unsigned short a) { > > asm("myinstr my16bitreg, %0"::"r"(a)); > > } > > I want it generate instruction "myinstr my16bitreg, r15" > > > > I execute > > llc test.bc -march = msp430 -o test.s > > then it reports > > "LLVM ERROR: Couldn't alloca...

...PC Isel backend. I would like to fetch few instructions into one like that: def MatchPAT1 : Pat<(or (or (shl GPRC:$rA, (i32 imm:$imm24)), (and (shl GPRC:$rA, (i32 imm:$imm8)), 0xFF0000) ), (or (srl GPRC:$rA, (i32 imm:$imm24)), (and (shl GPRC:$rA, (i32 imm:$imm8)),0xFF00) )), (myinstr GPRC:$rA)>; That pattern corresponds to i32 bswap intrinsic. The thing is that such complex pattern matching does not work. I can specify really simple patterns like: shl GPRC:$rA, (i32 imm: $imm8) and they work fine but whenever I try to fetch something more complex like: (and (shl GPRC: $...

Hi all, I want to generate an assembly instruction for my target using target description representation of the instruction. The problem is that I want to add direct register to be chose as an output register for my target. Does it possible to do with an instruction definition in TARGETInstrInfo.td file? May be someone could help with an example? Currently I have seen that we can pass the name

On May 9, 2013, at 4:02 AM, Fraser Cormack <fraser at codeplay.com> wrote: > I have an instruction that takes no operands, and produces two results, in two consecutive cycles. > > I tried both of the following to my Schedule.td file: > > InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>, > InstrItinData<IIMyInstr, [InstrStage<1, [FuncU]>, InstrStage<1, [FuncU]>], [1, 2]>, > > From what I can see in examples, these say that the first operand is ready the cycle after issue, and the second is ready 2 cycles a...

...codeplay.com > <mailto:fraser at codeplay.com>> wrote: > >> I have an instruction that takes no operands, and produces two >> results, in two consecutive cycles. >> >> I tried both of the following to my Schedule.td file: >> >> InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>, >> InstrItinData<IIMyInstr, [InstrStage<1, [FuncU]>, InstrStage<1, >> [FuncU]>], [1, 2]>, >> >> From what I can see in examples, these say that the first operand is >> ready the cycle after issue, and...

Hi all, I'm trying to simulate an extended x86 architecture on gem5 with several new instructions. My hardware setup is done and now I'd like llvm to accept the existence of the new instruction passed in inline assembly and output the correct opcode and registers. I chose the two-byte opcode 0x0F 0x7A and I would like the instruction to have the same operands and return values as CVTPS2PI

I have an instruction that takes no operands, and produces two results, in two consecutive cycles. I tried both of the following to my Schedule.td file: InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>, InstrItinData<IIMyInstr, [InstrStage<1, [FuncU]>, InstrStage<1, [FuncU]>], [1, 2]>, From what I can see in examples, these say that the first operand is ready the cycle after issue, and the second is ready 2 cycles after issue....

...u can achieve this by creating a specialized singleton register class with the register you want and use it in the td file. > E.g., in yourTargetRegisterInfo.td: > def MyReg : RegisterClass<“MyTarget”, [Related Types], MySize, (add MyReg)>; > > in yourTargetInstrInfo.td: > def MyInstr […] (outs MyReg:$Rd) […] > > The ARM target does something similar for SP. Look for GPRsp. > If you use this approach, you may run into issues if the scheduler decides to put two instructions that write to this register class in a row. In this case you will either need to implement spi...

hi Tim,guys, it was regarding splitting 16-bit ADDC to two 8-bit ADDC+ADDE. the 8-bit ADDE instruction is defined as: let Constraints="$dst=$op0",mayStore=1, hasSideEffects=0,neverHasSideEffects=1 in def ADDErm: myInstr <0x0, (outs Intregs:$dst) (ins Intregs:$op0,MEMi:$op1), "", [set IntRegs:$dest (adde IntRegs:$op0, (load ADDRi:$op1))] > very unlucky, this instruction failed. in the generated match table, there was flag OPFL_Chain. it caused a token factor node to be created in switch case OPC...