search for: myinst

...nt to add a set of "properties" to each instruction in my instruction set, and want to be able to query that in my machine-specific optimizations. My Insts.td file looks as follows : class InstProperty; def propX : InstProperty; def propY : InstProperty; def propZ : InstProperty; class myInst<..., list<InstProperty> props> : Instruction { ... ... list<InstProperty> Properties=props; } def i1 : myInst<..., [propX]>; def i2 : myInst<..., [propX, propZ]>; def i3 : myInst<..., []>; I want to add a Tablegen backend that would look for Instructions...

...ut now i am in the black hole. 1/ The story begins with this use of smbclient: sgi 18% /usr/samba/bin/smbclient \\\\kiowa\\C$ -U Administrateur added interface ip=10.44.0.40 bcast=10.44.0.255 nmask=255.255.255.0 Password: Domain=[IRCN] OS=[Windows NT 4.0] Server=[NT LAN Manager 4.0] smb: \> cd myinst smb: \myinst\> archive 0 smb: \myinst\> tarmode quiet tarmode is now full, system, hidden, noreset, quiet smb: \myinst\> tar c inst1.tar tar: dumped 632 files and directories Total bytes written: 182655488 smb: \myinst\> archive 0 smb: \myinst\> tarmode quiet tarmode is now full, sys...

...ch instruction in my > instruction set, and want to be able to query that in my > machine-specific optimizations. My Insts.td file looks as follows : > > class InstProperty; > > def propX : InstProperty; > def propY : InstProperty; > def propZ : InstProperty; > > class myInst<..., list<InstProperty> props> : Instruction { > ... > ... > list<InstProperty> Properties=props; > } > > def i1 : myInst<..., [propX]>; > def i2 : myInst<..., [propX, propZ]>; > def i3 : myInst<..., []>; > > I want to add a Ta...

Hi LLVM, I ran into a case where RegAlloc would insert a spill across instruction that had same register for output operand and implicit-def. The effect this had was that spill code would immediately overwrite the output result. Is this the expected result of setting up MyInst this way? In other words, does RegAlloc know to not insert spill in case it sees that output reg is same as one of implicit-def? If this is intended (always spilling live regs across implicit-def inst?), I am puzzled on how to use MyInst that has variable output reg with static implicit-defs....

Hi Quentin, MyInst is a custom instruction that has implicit-defs of fixed registers. The implicit-defs are seen at the end of Instruction Selection. I'd like to add a report, but I am working on an out-of-tree backend based on 7.0. I can try to help reduce the testcase down. Filed https://bugs.llvm.org/show_bu...

...takes some work from the vector units and gives it to the scalar units, for load balancing purposes. In that pass, I need to convert some vector instructions in to a sequence of scalar instructions. For this, I need to know what scalar instruction to generate for a vector instruction. For example, myInst::AddV4 should become 4 myInst::Add, etc. I need this opcode->opcode map, that can provide me this information for all vector instructions. One way I can think of is, put this information along with the vector instruction description in the .td file. class vecInst<...,myInst s> : myInst&l...

...the shuffle mask in the machine instruction but sometimes if a vector_shuffle can only return LHS or RHS, it's removed/combined so that I cannot match vector_shuffle in the instruction selector. If the vector_shuffle is combined, I have to write the instruction selector like these: def SUBvv: MyInst<(ins REG:$src0, imm:$mask0, REG:$src1, imm:$mask1), [sub (vector_shuffle REG:$src0, REG:$src0, imm:$mask0), (vector_shuffle REG:$src1, REG:$src1, imm:$mask1)] def SUBrv: MyInst<(ins REG:$src0, REG:$src1, imm:$mask1), [sub REG:$src0, (vector_sh...

...e with the CodeGen expectation. Could anybody please help? Here is the example: I want to emit instruction for adding 2 different kind of oprands. Basically i want to mix register types when I define the instruction for add,sub etc I define the instruction TargetInstruction.td as follows: class MyInst <opcode op,subopcode subop, dag outs, dag ins, string asmstr,list<dag> pattern> Instruction { let Namespce = "MyNameSpace"; MyOpCode myop = op; MySubOpcode mysubop = subop; dag OutOprandList = outs; dag InOprandList = ins; let ASMString = asmstr; let Patter...

This sounds great! I've been bitten in the past by trying to use a single class for multiple types. Would it make sense to extend this to all DAG patterns? If I have an instruction def: def ANDN64 : MyInst<(outs Reg64:$d), (ins Reg64:$a, Reg64:$b), "and.64 $d, $a, $b", [(set Reg64:$d, (and (not (Reg64:$a, Reg64:$b))))]>; would I now be able to write: def ANDN64 : MyInst<(outs Reg64:$d), (ins Reg64:$a, Reg64:$b), "and.64 $d, $a, $b", [(set i64:$d, (and (not (i64:$a, i64:...

...ret Currently my ADD instruction is defined in the InstrInfo.td file as following: def I32RC : RegisterClass<"MyMachine", [i32], 32, [DefReg]>; def P32RC : RegisterClass<"MyMachine", [iPTR], 32, [DefReg]>; -> I get error from tablegen if I use iPTR def MyAdd : MyInst < myadd, nosubop, (outs I32RC:$dst), (ins I32RC:$src1, I32RC:$src2), “add $dst, $src1, $src2", [(set rc:$dst, (add I32RC:$src1, I32RC:$src2))] def MyPointerAdd : MyInst < mypointeradd, nosubop, (outs P32RC:$dst), (ins P32RC:$src1, P32RC:$src2), “pointer_add $dst, $src1, $src2&q...

Hi Jacob, thank you for your reply. Your suggestion works! But instead of using the Pat<>, I am using def MOVE_ADDR : MYInst<(outs Int32Regs:$dst), (ins i32mem:$a), "move $dst, $a;", [(set Int32Regs:$dst, (Wrapper tglobaladdr:$a))]>; I don't quite understand what the semantics of Pat in general. Could you please explain what def : Pat<(BfinWrapper (i32 t...

...2], 32, (add R0)>; def GPRr1 : RegisterClass<"FOO", [i32], 32, (add R1)>; def GPRr2 : RegisterClass<"FOO", [i32], 32, (add R2)>; The an instruction that uses R0 and R1 as fixed input registers and R2 for output could define itself using those register classs: def myInst : baseclass<…, (outs GPRr2:$dst), (ins GPRr0:$src1, GPRr1:$src2), …> Use those reg classes in pattern to match also, and things should just work. The register allocator can take care of any reg-to-reg copies that are required. -Jim

...ret Currently my ADD instruction is defined in the InstrInfo.td file as following: def I32RC : RegisterClass<"MyMachine", [i32], 32, [DefReg]>; def P32RC : RegisterClass<"MyMachine", [iPTR], 32, [DefReg]>; -> I get error from tablegen if I use iPTR def MyAdd : MyInst < myadd, nosubop, (outs I32RC:$dst), (ins I32RC:$src1, I32RC:$src2), “add $dst, $src1, $src2", [(set rc:$dst, (add I32RC:$src1, I32RC:$src2))] def MyPointerAdd : MyInst < mypointeradd, nosubop, (outs P32RC:$dst), (ins P32RC:$src1, P32RC:$src2), “pointer_add $dst, $src1, $src2"...

Jim, > The an instruction that uses R0 and R1 as fixed input registers and R2 for output could define itself using those register classs: > def myInst : baseclass<…, (outs GPRr2:$dst), (ins GPRr0:$src1, GPRr1:$src2), …> > Use those reg classes in pattern to match also, and things should just work. The register allocator can take care of any reg-to-reg copies that are required. As far as I understand Jonas, this does not work in his case....

...write a tablegen backend for something very specific to a target? The examples I gave happen to be applicable to many targets. But the usage depends on AN implementation of codegen for a target, no? I mean, I could choose to put the related scalar instruction in a field with a specific name in the myInst class in the .td file, and would want to populate a data structure with a specific name in my C++ code. The tablegen backend should "know" the names of both the field in the .td file and the name of the data structure. How can I make this generic? Thanks, Manjunath

For example, if you have something like: .... vreg3 = LD operation vreg4 = vreg2 * vreg1 ... Where I would like vreg3 and vreg4 to map to the same physical register? Imagine that the second instruction has an implicit arithmetic operation tied to vreg 4 such that vreg4 is both an input and output and the initial value of vreg4 is loaded into vreg3, so such that vreg4 = vreg3. Is this possible

You could hardcode a register for the pseudo instruction to use in the td file. The register allocator will make sure not to clobber it. let uses = [ R1 ], defs = [ R1 ] in { def MYINST : Pseudo<> } On Wed, Dec 11, 2019 at 10:25 AM Przemyslaw Ossowski via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I have one more question regarding expanding pseudo instruction. > > These two Machine Instructions, which I mentioned earlier, have to be one after anothe...

...r of the operands. This way tablegen can emit an error if the field name and operand name fail to match rather than silently producing an incorrect GenCodeEmitter. class MyFormat<bits<32> OpcVal, dag ops, string asmstr, list<dag> pattern, InstrItinClass itin> : MyInst<ops, asmstr, pattern, itin> { let Inst{31-28} = OpcVal{31-28}; bits<6> Rsrc1; <===== Because destination is required first in operand ordering, bits<6> Rdest; <===== this ordering of declarations produces an incorrect GenCodeEmitter bits<16> Imm16;...

----- Original Message ----- > From: "Jakob Stoklund Olesen" <stoklund at 2pi.dk> > To: llvmdev at cs.uiuc.edu, llvmdev at cs.uiuc.edu, llvmdev at cs.uiuc.edu, llvmdev at cs.uiuc.edu > Sent: Thursday, March 21, 2013 1:26:25 PM > Subject: [LLVMdev] Simpler types in TableGen isel patterns > > Currently, instruction selection patterns are defined like this: >

Dan, > In general, it's a design goal to structure CodeGen features as > target-independent code parameterized with target-specific data. > The degree to which this goal is met in LLVM CodeGen features today > varies, but features that have been implemented using TableGen have > been relatively successful. Can you give an example of a relatively successful instance where