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The attached patch fixes the save/restore issue seen with 32bit Windows guest VMs. The root cause is that current Xen doesn''t intercept SYSENTER-related MSRs for 32bit guest VMs. As a result, the guest_sysenter_xxx fields contain incorrect values and shouldn''t be used for save/restore. This patch checks the LMA bit of EFER register in the save/restore code path. Please apply it to both Xen-4.0 and Xen-unstable trees. Reported-by: James Harper...

On 25/09/2017 06:44, Wei Wang wrote: > > +static void update_msr_autoload_count_max(void) > +{ > + u64 vmx_msr; > + int n; > + > + /* > + * According to the Intel SDM, if Bits 27:25 of MSR_IA32_VMX_MISC is > + * n, then (n + 1) * 512 is the recommended max number of MSRs to be > + * included in the VMExit and VMEntry MSR auto switch list. > + */ > + rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); > + n = ((vmx_msr & 0xe000000) >> 25) + 1; > + msr_autoload_count_max = n * KVM_VMX_DEFAULT_MSR_AUTO_LOAD_COUNT; > +} > + Any reasons to do this if...

On 25/09/2017 06:44, Wei Wang wrote: > > +static void update_msr_autoload_count_max(void) > +{ > + u64 vmx_msr; > + int n; > + > + /* > + * According to the Intel SDM, if Bits 27:25 of MSR_IA32_VMX_MISC is > + * n, then (n + 1) * 512 is the recommended max number of MSRs to be > + * included in the VMExit and VMEntry MSR auto switch list. > + */ > + rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); > + n = ((vmx_msr & 0xe000000) >> 25) + 1; > + msr_autoload_count_max = n * KVM_VMX_DEFAULT_MSR_AUTO_LOAD_COUNT; > +} > + Any reasons to do this if...

...or the cross-HV mechanism, but we can't do that without either knowingly violating the SDM assignments or asking Intel to consider allocating more MSR indexes. Also, KVM is already conflicting with the SDM right now in its MSR choice :( I *think* that KVM could be changed to fix that, but 256 MSRs is rather confining given that KVM currently implements its own MSR index *and* part of the Hyper-V index. --Andy

...or the cross-HV mechanism, but we can't do that without either knowingly violating the SDM assignments or asking Intel to consider allocating more MSR indexes. Also, KVM is already conflicting with the SDM right now in its MSR choice :( I *think* that KVM could be changed to fix that, but 256 MSRs is rather confining given that KVM currently implements its own MSR index *and* part of the Hyper-V index. --Andy

From: Mihai Don?u <mdontu at bitdefender.com> This command is used to get kvm_regs and kvm_sregs structures, plus the list of struct kvm_msrs. Signed-off-by: Mihai Don?u <mdontu at bitdefender.com> Co-developed-by: Adalbert Laz?r <alazar at bitdefender.com> Signed-off-by: Adalbert Laz?r <alazar at bitdefender.com> --- Documentation/virt/kvm/kvmi.rst | 42 +++++++++++ arch/x86/include/uapi/asm/kvmi.h...

This patch is based on Rusty's recent cleanup of the EFLAGS-related macros; it extends the same kind of cleanup to control registers and MSRs. It also unifies these between i386 and x86-64; at least with regards to MSRs, the two had definitely gotten out of sync. Signed-off-by: H. Peter Anvin <hpa@zytor.com> diff -urN --exclude='o.*' --exclude '*~' stock/linux-2.6.21-rc6-mm1/include/asm-i386/Kbuild linux-2.6.21-r...

This patch is based on Rusty's recent cleanup of the EFLAGS-related macros; it extends the same kind of cleanup to control registers and MSRs. It also unifies these between i386 and x86-64; at least with regards to MSRs, the two had definitely gotten out of sync. Signed-off-by: H. Peter Anvin <hpa@zytor.com> diff -urN --exclude='o.*' --exclude '*~' stock/linux-2.6.21-rc6-mm1/include/asm-i386/Kbuild linux-2.6.21-r...

From: Mihai Don?u <mdontu at bitdefender.com> This command is used to get kvm_regs and kvm_sregs structures, plus a list of struct kvm_msrs from a specific vCPU. While the kvm_regs and kvm_sregs structures are included with every event, this command allows reading any MSR and can be used as a quick way to read the state of any vCPU. Signed-off-by: Mihai Don?u <mdontu at bitdefender.com> Co-developed-by: Adalbert Laz?r <alaza...

[PATCH] Clean up x86 control register and MSR macros This patch is based on Rusty's recent cleanup of the EFLAGS-related macros; it extends the same kind of cleanup to control registers and MSRs. It also unifies these between i386 and x86-64; at least with regards to MSRs, the two had definitely gotten out of sync. Signed-off-by: H. Peter Anvin <hpa@zytor.com> diff -urN --exclude='o.*' stock/linux-2.6.21-rc6-mm1/include/asm-i386/Kbuild linux-2.6.21-rc6-mm1/include/asm-i386...

[PATCH] Clean up x86 control register and MSR macros This patch is based on Rusty's recent cleanup of the EFLAGS-related macros; it extends the same kind of cleanup to control registers and MSRs. It also unifies these between i386 and x86-64; at least with regards to MSRs, the two had definitely gotten out of sync. Signed-off-by: H. Peter Anvin <hpa@zytor.com> diff -urN --exclude='o.*' stock/linux-2.6.21-rc6-mm1/include/asm-i386/Kbuild linux-2.6.21-rc6-mm1/include/asm-i386...

This patch adds the MTRR MSRs save/restore support. Signed-off-by: Disheng Su <disheng.su@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Hello, I recently tried Xen 3.0.3-testing on my 2x Opteron-244 SMP machine. Everything works well exept one detail, which is not unimportant to me: the powernow-k8 driver fails to switch frequencies. A closer look on the powernow-k8 source reveals, that some MSR write operations seem to be without any effect. A rdmsr() before and after the wrmsr() call reveals that no real change on the register

...18, 2014 at 9:36 AM, KY Srinivasan <kys at microsoft.com> wrote: > > I am copying other Hyper-V engineers to this discussion. > Thanks, K.Y. In terms of the address for the MSR, I suggest that you choose one from the range between 40000000H - 400000FFH. The SDM (35.1 ARCHITECTURAL MSRS) says "All existing and future processors will not implement any features using any MSR in this range." Hyper-V already defines many synthetic MSRs in this range, and I think it would be reasonable for you to pick one for this to avoid a conflict? -- Jun Intel Open Source Technology Cen...

...18, 2014 at 9:36 AM, KY Srinivasan <kys at microsoft.com> wrote: > > I am copying other Hyper-V engineers to this discussion. > Thanks, K.Y. In terms of the address for the MSR, I suggest that you choose one from the range between 40000000H - 400000FFH. The SDM (35.1 ARCHITECTURAL MSRS) says "All existing and future processors will not implement any features using any MSR in this range." Hyper-V already defines many synthetic MSRs in this range, and I think it would be reasonable for you to pick one for this to avoid a conflict? -- Jun Intel Open Source Technology Cen...

This patch series enables the Last Branch Recording feature for the guest. Instead of trapping each LBR stack MSR access, the MSRs are passthroughed to the guest. Those MSRs are switched (i.e. load and saved) on VMExit and VMEntry. Test: Try "perf record -b ./test_program" on guest. Wei Wang (4): KVM/vmx: re-write the msr auto switch feature KVM/vmx: auto switch MSR_IA32_DEBUGCTLMSR perf/x86: add a function t...

This patch series enables the Last Branch Recording feature for the guest. Instead of trapping each LBR stack MSR access, the MSRs are passthroughed to the guest. Those MSRs are switched (i.e. load and saved) on VMExit and VMEntry. Test: Try "perf record -b ./test_program" on guest. Wei Wang (4): KVM/vmx: re-write the msr auto switch feature KVM/vmx: auto switch MSR_IA32_DEBUGCTLMSR perf/x86: add a function t...

Could anyone summarize what the support status of cpu frequency changes is at present. I don''t seem to recall generic changes to the hpyervisor in that respect, but the linux tree has fairly extensive changes to the powernow-k8 driver (which would make sense to me only if all other cpufreq drivers are fully supported now, too). Thanks, Jan

...: >> >> +static void update_msr_autoload_count_max(void) >> +{ >> + u64 vmx_msr; >> + int n; >> + >> + /* >> + * According to the Intel SDM, if Bits 27:25 of MSR_IA32_VMX_MISC is >> + * n, then (n + 1) * 512 is the recommended max number of MSRs to be >> + * included in the VMExit and VMEntry MSR auto switch list. >> + */ >> + rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); >> + n = ((vmx_msr & 0xe000000) >> 25) + 1; >> + msr_autoload_count_max = n * KVM_VMX_DEFAULT_MSR_AUTO_LOAD_COUNT; >> +} >> +...

Propagate guest MSR writes to machine MSRs immediately Right now, we have an exposure between the time the MSR is written and used by an instruction such as syscall. If there is a context switch and we do vmx_do_restore_msrs(), everything goes fine. But if we don''t, then we execute the syscall with the wrong MSR. Signed-off-by: Y...