search for: msr_ia32_therm_control

Displaying 6 results from an estimated 6 matches for "msr_ia32_therm_control".

[PATCH 2/2] ACPI: Grant access of MSR_IA32_THERM_CONTROL MSR to dom0
2008 Sep 11
0
[PATCH 2/2] ACPI: Grant access of MSR_IA32_THERM_CONTROL MSR to dom0
ACPI: Grant access of MSR_IA32_THERM_CONTROL MSR to dom0 The purpose is to support dom0 throttling control via MSR. Signed-off-by: Wei Gang <gang.wei@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
[PATCH 4/4] ACPI: Enable THERM_CONTROL MSR write for dom0 even cpufreq=xen
2009 Feb 26
5
[PATCH 4/4] ACPI: Enable THERM_CONTROL MSR write for dom0 even cpufreq=xen
...TL: + if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ) + goto fail; + if ( !is_cpufreq_controller(v->domain) ) + break; + if ( wrmsr_safe(regs->ecx, eax, edx) != 0 ) + goto fail; + break; case MSR_IA32_THERM_CONTROL: if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ) goto fail; - if ( !is_cpufreq_controller(v->domain) ) + if ( d->domain_id != 0 ) break; if ( wrmsr_safe(regs->ecx, eax, edx) != 0 ) goto f...
[PATCH] Clean up x86 control register and MSR macros (corrected)
2007 Apr 18
2
[PATCH] Clean up x86 control register and MSR macros (corrected)
...00000189 +#define MSR_IA32_MCG_RESERVED 0x0000018a + +#define MSR_P6_EVNTSEL0 0x00000186 +#define MSR_P6_EVNTSEL1 0x00000187 + +#define MSR_IA32_PERF_STATUS 0x00000198 +#define MSR_IA32_PERF_CTL 0x00000199 + +#define MSR_IA32_MPERF 0x000000e7 +#define MSR_IA32_APERF 0x000000e8 + +#define MSR_IA32_THERM_CONTROL 0x0000019a +#define MSR_IA32_THERM_INTERRUPT 0x0000019b +#define MSR_IA32_THERM_STATUS 0x0000019c +#define MSR_IA32_MISC_ENABLE 0x000001a0 + +/* Pentium IV performance counter MSRs */ +#define MSR_P4_BPU_PERFCTR0 0x00000300 +#define MSR_P4_BPU_PERFCTR1 0x00000301 +#define MSR_P4_BPU_PERFCTR2...
[PATCH] Clean up x86 control register and MSR macros (corrected)
2007 Apr 18
2
[PATCH] Clean up x86 control register and MSR macros (corrected)
...00000189 +#define MSR_IA32_MCG_RESERVED 0x0000018a + +#define MSR_P6_EVNTSEL0 0x00000186 +#define MSR_P6_EVNTSEL1 0x00000187 + +#define MSR_IA32_PERF_STATUS 0x00000198 +#define MSR_IA32_PERF_CTL 0x00000199 + +#define MSR_IA32_MPERF 0x000000e7 +#define MSR_IA32_APERF 0x000000e8 + +#define MSR_IA32_THERM_CONTROL 0x0000019a +#define MSR_IA32_THERM_INTERRUPT 0x0000019b +#define MSR_IA32_THERM_STATUS 0x0000019c +#define MSR_IA32_MISC_ENABLE 0x000001a0 + +/* Pentium IV performance counter MSRs */ +#define MSR_P4_BPU_PERFCTR0 0x00000300 +#define MSR_P4_BPU_PERFCTR1 0x00000301 +#define MSR_P4_BPU_PERFCTR2...
No subject
2007 Apr 18
1
No subject
...00000189 +#define MSR_IA32_MCG_RESERVED 0x0000018a + +#define MSR_P6_EVNTSEL0 0x00000186 +#define MSR_P6_EVNTSEL1 0x00000187 + +#define MSR_IA32_PERF_STATUS 0x00000198 +#define MSR_IA32_PERF_CTL 0x00000199 + +#define MSR_IA32_MPERF 0x000000e7 +#define MSR_IA32_APERF 0x000000e8 + +#define MSR_IA32_THERM_CONTROL 0x0000019a +#define MSR_IA32_THERM_INTERRUPT 0x0000019b +#define MSR_IA32_THERM_STATUS 0x0000019c +#define MSR_IA32_MISC_ENABLE 0x000001a0 + +/* Pentium IV performance counter MSRs */ +#define MSR_P4_BPU_PERFCTR0 0x00000300 +#define MSR_P4_BPU_PERFCTR1 0x00000301 +#define MSR_P4_BPU_PERFCTR2...
No subject
2007 Apr 18
1
No subject
...00000189 +#define MSR_IA32_MCG_RESERVED 0x0000018a + +#define MSR_P6_EVNTSEL0 0x00000186 +#define MSR_P6_EVNTSEL1 0x00000187 + +#define MSR_IA32_PERF_STATUS 0x00000198 +#define MSR_IA32_PERF_CTL 0x00000199 + +#define MSR_IA32_MPERF 0x000000e7 +#define MSR_IA32_APERF 0x000000e8 + +#define MSR_IA32_THERM_CONTROL 0x0000019a +#define MSR_IA32_THERM_INTERRUPT 0x0000019b +#define MSR_IA32_THERM_STATUS 0x0000019c +#define MSR_IA32_MISC_ENABLE 0x000001a0 + +/* Pentium IV performance counter MSRs */ +#define MSR_P4_BPU_PERFCTR0 0x00000300 +#define MSR_P4_BPU_PERFCTR1 0x00000301 +#define MSR_P4_BPU_PERFCTR2...