Displaying 20 results from an estimated 22 matches for "msix_table_page".
2009 Jun 02
0
[PATCHv2 05/13] qemu: MSI-X support functions
...t; enable_pos)
+ return;
+
+ if (msix_enabled(dev))
+ qemu_set_irq(dev->irq[0], 0);
+}
+
+static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ PCIDevice *dev = opaque;
+ unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
+ void *page = dev->msix_table_page;
+ uint32_t val = 0;
+
+ memcpy(&val, (void *)((char *)page + offset), 4);
+
+ return val;
+}
+
+static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
+{
+ fprintf(stderr, "MSI-X: only dword read is allowed!\n");
+ return 0;
+}
+
+static uint8_...
2009 Jun 02
0
[PATCHv2 05/13] qemu: MSI-X support functions
...t; enable_pos)
+ return;
+
+ if (msix_enabled(dev))
+ qemu_set_irq(dev->irq[0], 0);
+}
+
+static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ PCIDevice *dev = opaque;
+ unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
+ void *page = dev->msix_table_page;
+ uint32_t val = 0;
+
+ memcpy(&val, (void *)((char *)page + offset), 4);
+
+ return val;
+}
+
+static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
+{
+ fprintf(stderr, "MSI-X: only dword read is allowed!\n");
+ return 0;
+}
+
+static uint8_...
2009 May 25
1
[PATCH 05/11] qemu: MSI-X support functions
...t; enable_pos)
+ return;
+
+ if (msix_enabled(dev))
+ qemu_set_irq(dev->irq[0], 0);
+}
+
+static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ PCIDevice *dev = opaque;
+ unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
+ void *page = dev->msix_table_page;
+ uint32_t val = 0;
+
+ memcpy(&val, (void *)((char *)page + offset), 4);
+
+ return val;
+}
+
+static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
+{
+ fprintf(stderr, "MSI-X: only dword read is allowed!\n");
+ return 0;
+}
+
+static uint8_...
2009 May 25
1
[PATCH 05/11] qemu: MSI-X support functions
...t; enable_pos)
+ return;
+
+ if (msix_enabled(dev))
+ qemu_set_irq(dev->irq[0], 0);
+}
+
+static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ PCIDevice *dev = opaque;
+ unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
+ void *page = dev->msix_table_page;
+ uint32_t val = 0;
+
+ memcpy(&val, (void *)((char *)page + offset), 4);
+
+ return val;
+}
+
+static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
+{
+ fprintf(stderr, "MSI-X: only dword read is allowed!\n");
+ return 0;
+}
+
+static uint8_...
2009 Jun 21
1
[PATCHv6 05/12] qemu/pci: MSI-X support functions
...t; enable_pos)
+ return;
+
+ if (msix_enabled(dev))
+ qemu_set_irq(dev->irq[0], 0);
+}
+
+static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ PCIDevice *dev = opaque;
+ unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
+ void *page = dev->msix_table_page;
+ uint32_t val = 0;
+
+ memcpy(&val, (void *)((char *)page + offset), 4);
+
+ return val;
+}
+
+static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
+{
+ fprintf(stderr, "MSI-X: only dword read is allowed!\n");
+ return 0;
+}
+
+static uint8_...
2009 Jun 21
1
[PATCHv6 05/12] qemu/pci: MSI-X support functions
...t; enable_pos)
+ return;
+
+ if (msix_enabled(dev))
+ qemu_set_irq(dev->irq[0], 0);
+}
+
+static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ PCIDevice *dev = opaque;
+ unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
+ void *page = dev->msix_table_page;
+ uint32_t val = 0;
+
+ memcpy(&val, (void *)((char *)page + offset), 4);
+
+ return val;
+}
+
+static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
+{
+ fprintf(stderr, "MSI-X: only dword read is allowed!\n");
+ return 0;
+}
+
+static uint8_...
2009 Jun 18
0
[PATCHv5 05/13] qemu: MSI-X support functions
...t; enable_pos)
+ return;
+
+ if (msix_enabled(dev))
+ qemu_set_irq(dev->irq[0], 0);
+}
+
+static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ PCIDevice *dev = opaque;
+ unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
+ void *page = dev->msix_table_page;
+ uint32_t val = 0;
+
+ memcpy(&val, (void *)((char *)page + offset), 4);
+
+ return val;
+}
+
+static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
+{
+ fprintf(stderr, "MSI-X: only dword read is allowed!\n");
+ return 0;
+}
+
+static uint8_...
2009 Jun 18
0
[PATCHv5 05/13] qemu: MSI-X support functions
...t; enable_pos)
+ return;
+
+ if (msix_enabled(dev))
+ qemu_set_irq(dev->irq[0], 0);
+}
+
+static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ PCIDevice *dev = opaque;
+ unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
+ void *page = dev->msix_table_page;
+ uint32_t val = 0;
+
+ memcpy(&val, (void *)((char *)page + offset), 4);
+
+ return val;
+}
+
+static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
+{
+ fprintf(stderr, "MSI-X: only dword read is allowed!\n");
+ return 0;
+}
+
+static uint8_...
2009 Jun 10
0
[PATCHv4 05/13] qemu: MSI-X support functions
...t; enable_pos)
+ return;
+
+ if (msix_enabled(dev))
+ qemu_set_irq(dev->irq[0], 0);
+}
+
+static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ PCIDevice *dev = opaque;
+ unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
+ void *page = dev->msix_table_page;
+ uint32_t val = 0;
+
+ memcpy(&val, (void *)((char *)page + offset), 4);
+
+ return val;
+}
+
+static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
+{
+ fprintf(stderr, "MSI-X: only dword read is allowed!\n");
+ return 0;
+}
+
+static uint8_...
2009 Jun 10
0
[PATCHv4 05/13] qemu: MSI-X support functions
...t; enable_pos)
+ return;
+
+ if (msix_enabled(dev))
+ qemu_set_irq(dev->irq[0], 0);
+}
+
+static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ PCIDevice *dev = opaque;
+ unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
+ void *page = dev->msix_table_page;
+ uint32_t val = 0;
+
+ memcpy(&val, (void *)((char *)page + offset), 4);
+
+ return val;
+}
+
+static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
+{
+ fprintf(stderr, "MSI-X: only dword read is allowed!\n");
+ return 0;
+}
+
+static uint8_...
2009 Jun 05
1
[PATCHv3 05/13] qemu: MSI-X support functions
...t; enable_pos)
+ return;
+
+ if (msix_enabled(dev))
+ qemu_set_irq(dev->irq[0], 0);
+}
+
+static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ PCIDevice *dev = opaque;
+ unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
+ void *page = dev->msix_table_page;
+ uint32_t val = 0;
+
+ memcpy(&val, (void *)((char *)page + offset), 4);
+
+ return val;
+}
+
+static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
+{
+ fprintf(stderr, "MSI-X: only dword read is allowed!\n");
+ return 0;
+}
+
+static uint8_...
2009 Jun 05
1
[PATCHv3 05/13] qemu: MSI-X support functions
...t; enable_pos)
+ return;
+
+ if (msix_enabled(dev))
+ qemu_set_irq(dev->irq[0], 0);
+}
+
+static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
+{
+ PCIDevice *dev = opaque;
+ unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
+ void *page = dev->msix_table_page;
+ uint32_t val = 0;
+
+ memcpy(&val, (void *)((char *)page + offset), 4);
+
+ return val;
+}
+
+static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
+{
+ fprintf(stderr, "MSI-X: only dword read is allowed!\n");
+ return 0;
+}
+
+static uint8_...
2009 May 20
0
[PATCHv2-RFC 1/2] qemu-kvm: add MSI-X support
...able(PCIDevice *dev)
+{
+ uint32_t ctrl, data;
+ int i;
+
+ if (!dev->msix_irq_entries_nr) {
+ fprintf(stderr, "MSI-X entry number is zero!\n");
+ return;
+ }
+
+ for (i = 0; i < dev->msix_irq_entries_nr; ++i) {
+ uint8_t *table_entry = dev->msix_table_page + i * MSIX_ENTRY_SIZE;
+
+ data = pci_get_long(table_entry + MSIX_MSG_DATA);
+ if (!data)
+ msix_vector_unuse(dev, i);
+ else
+ msix_vector_use(dev, i);
+ }
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32...
2009 May 20
0
[PATCHv2-RFC 1/2] qemu-kvm: add MSI-X support
...able(PCIDevice *dev)
+{
+ uint32_t ctrl, data;
+ int i;
+
+ if (!dev->msix_irq_entries_nr) {
+ fprintf(stderr, "MSI-X entry number is zero!\n");
+ return;
+ }
+
+ for (i = 0; i < dev->msix_irq_entries_nr; ++i) {
+ uint8_t *table_entry = dev->msix_table_page + i * MSIX_ENTRY_SIZE;
+
+ data = pci_get_long(table_entry + MSIX_MSG_DATA);
+ if (!data)
+ msix_vector_unuse(dev, i);
+ else
+ msix_vector_use(dev, i);
+ }
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32...
2009 May 20
0
[PATCHv2-RFC 2/2] qemu-kvm: use common code for assigned msix
...= container_of(pci_dev, AssignedDevice, dev);
- u16 entries_nr = 0, entries_max_nr;
- int pos = 0, i, r = 0;
- u32 msg_addr, msg_upper_addr, msg_data, msg_ctrl;
+ int i, r;
struct kvm_assigned_msix_nr msix_nr;
struct kvm_assigned_msix_entry msix_entry;
- void *va = adev->msix_table_page;
-
- if (adev->cap.available & ASSIGNED_DEVICE_CAP_MSI)
- pos = pci_dev->cap.start + PCI_CAPABILITY_CONFIG_MSI_LENGTH;
- else
- pos = pci_dev->cap.start;
-
- entries_max_nr = pci_dev->config[pos + 2];
- entries_max_nr &= PCI_MSIX_TABSIZE;
- entries_m...
2009 May 20
0
[PATCHv2-RFC 2/2] qemu-kvm: use common code for assigned msix
...= container_of(pci_dev, AssignedDevice, dev);
- u16 entries_nr = 0, entries_max_nr;
- int pos = 0, i, r = 0;
- u32 msg_addr, msg_upper_addr, msg_data, msg_ctrl;
+ int i, r;
struct kvm_assigned_msix_nr msix_nr;
struct kvm_assigned_msix_entry msix_entry;
- void *va = adev->msix_table_page;
-
- if (adev->cap.available & ASSIGNED_DEVICE_CAP_MSI)
- pos = pci_dev->cap.start + PCI_CAPABILITY_CONFIG_MSI_LENGTH;
- else
- pos = pci_dev->cap.start;
-
- entries_max_nr = pci_dev->config[pos + 2];
- entries_max_nr &= PCI_MSIX_TABSIZE;
- entries_m...
2009 May 11
0
[PATCH 2/2] qemu-kvm: use common code for assigned msix
..._of(pci_dev, AssignedDevice, dev);
- u16 entries_nr = 0, entries_max_nr;
- int pos = 0, i, r = 0;
- u32 msg_addr, msg_upper_addr, msg_data, msg_ctrl;
+ int i, r = 0, n = 0;
struct kvm_assigned_msix_nr msix_nr;
struct kvm_assigned_msix_entry msix_entry;
- void *va = adev->msix_table_page;
-
- if (adev->cap.available & ASSIGNED_DEVICE_CAP_MSI)
- pos = pci_dev->cap.start + PCI_CAPABILITY_CONFIG_MSI_LENGTH;
- else
- pos = pci_dev->cap.start;
-
- entries_max_nr = pci_dev->config[pos + 2];
- entries_max_nr &= PCI_MSIX_TABSIZE;
- entries_m...
2009 May 11
0
[PATCH 2/2] qemu-kvm: use common code for assigned msix
..._of(pci_dev, AssignedDevice, dev);
- u16 entries_nr = 0, entries_max_nr;
- int pos = 0, i, r = 0;
- u32 msg_addr, msg_upper_addr, msg_data, msg_ctrl;
+ int i, r = 0, n = 0;
struct kvm_assigned_msix_nr msix_nr;
struct kvm_assigned_msix_entry msix_entry;
- void *va = adev->msix_table_page;
-
- if (adev->cap.available & ASSIGNED_DEVICE_CAP_MSI)
- pos = pci_dev->cap.start + PCI_CAPABILITY_CONFIG_MSI_LENGTH;
- else
- pos = pci_dev->cap.start;
-
- entries_max_nr = pci_dev->config[pos + 2];
- entries_max_nr &= PCI_MSIX_TABSIZE;
- entries_m...
2009 May 11
0
[PATCH 1/2] qemu-kvm: add MSI-X support
...able(PCIDevice *dev)
+{
+ uint32_t ctrl, data;
+ int i;
+
+ if (!dev->msix_irq_entries_nr) {
+ fprintf(stderr, "MSI-X entry number is zero!\n");
+ return;
+ }
+
+ for (i = 0; i < dev->msix_irq_entries_nr; ++i) {
+ uint8_t *table_entry = dev->msix_table_page + i * MSIX_ENTRY_SIZE;
+
+ /* FIXME: move this to pio handling code */
+ ctrl = pci_get_long(table_entry + MSIX_VECTOR_CTRL);
+ data = pci_get_long(table_entry + MSIX_MSG_DATA);
+ if ((ctrl & MSIX_VECTOR_MASK) || !data)
+ msix_vector_unuse(dev, i);
+ else...
2009 May 11
0
[PATCH 1/2] qemu-kvm: add MSI-X support
...able(PCIDevice *dev)
+{
+ uint32_t ctrl, data;
+ int i;
+
+ if (!dev->msix_irq_entries_nr) {
+ fprintf(stderr, "MSI-X entry number is zero!\n");
+ return;
+ }
+
+ for (i = 0; i < dev->msix_irq_entries_nr; ++i) {
+ uint8_t *table_entry = dev->msix_table_page + i * MSIX_ENTRY_SIZE;
+
+ /* FIXME: move this to pio handling code */
+ ctrl = pci_get_long(table_entry + MSIX_VECTOR_CTRL);
+ data = pci_get_long(table_entry + MSIX_MSG_DATA);
+ if ((ctrl & MSIX_VECTOR_MASK) || !data)
+ msix_vector_unuse(dev, i);
+ else...